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RISC-V Summit 2022
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December 13-14, 2022 | San Jose, CA + Virtual
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Krishnakumar (KK)
Microchip
BA
Bruce Ableidinger
SiFive Inc.
Senior Architect
RA
Rob Aitken
Synopsys
Distinguished Architect
SA
Srikanth Arekapudi
Tenstorrent
Fellow
Krste Asanovic
RISC-V International
Chair
EA
Eve Atallah
NXP Semiconductors
Security Evaluation Expert
Balaji Baktha
Ventana Micro Systems
President & CEO
DB
Drew Barbier
SiFive
Senior Director of Product Marketing
Allen Baum
Esperanto Technologies, Inc.
Chair of RISC-V International Architecture Test SIG
Lars Bergstrom
Android Platform Programming Languages
Google Director of Engineering
OB
Olivier Bernard
AWS
IOT and Robotics Services
Luca Bertaccini
ETH Zürich
PhD Student
Ron Black
Codasip
CEO
BB
Bob Brennan
Intel
VP&GM Customer Solutions Engineering, Intel Foundry Services
AC
Arup Chakraborty
Ventana Microsystems
Sr. Staff Engineer
eop Chen
SiFive
Compiler Engineer
Tiejun Chen
VMware
Sr. Technical Lead
GC
Giorgos Christou
Forth
PhD student
Hubert Chung
Andes Technology
FAE Manager,
Xiaoxia Cui
Alibaba
IoT Security Expert
Simon Davidmann
Imperas Software
CEO
JD
John Davis
Barcelona Supercomputing Center
Director, Laboratory for Open Computer Architecture
Shreyas Derashri
Imagination Technologies
VP of Compute
Dave Ditzel
Esperanto Technologies
CTO
Ken Dockser
Rivos Inc.
CPU Architect
Leendert van Doorn
Qualcomm
SVP Engineering
JD
jiangang duan
Intel
RISC-V SW Engineering Director
AD
Aaron Durbin
Rivos Inc.
Principal Engineer
Phil Dworsky
SiFive
Head of Strategic Alliances
Paul Elliott
Codasip
Security and Safety Architect
Pete Fiacco
Member HPSC Leadership Team, JPL Consultant, Managing Partner,...
Neel Gala
Incore Semicoductor
CTO
Michael Gielda
Antmicro
Vice President, Business Development & Co-Founder
Nikhil Krishna Gopalakrishna
Intel
Principal Engineer
Keith Graham
Codasip
Vice President of University and Customer Experience Program
Dan Gross
AWS
Sr. Developer Advocate
Sam Grove
SiFive
Director Product Management - Software
Adnan Hamid
Breker Verification Systems
CTO
Mao Han
Alibaba
Senior Engineer
Sarah Harris
University of Nevada in Las Vegas
Professor
JH
john hengeveld
Intel
SW Product Management Director
Mark Himelstein
RISC-V International
CTO
Shenwei Hu
RIOS Lab, Tsinghua University
Master Student
AH
Amber Huffman
Google
Principal Engineer
Andrew Jones
Ventana Micro Systems Inc.
Principal Software Engineer
Olof Kindgren
Qamcom
Senior Digital Design Engineer
Andreas Koch
TU Darmstadt
Professor
Leonidas Kosmidis
Barcelona Supercomputing Center (BSC)
Senior Researcher
S Pawan Kumar
InCore Semicoductors
RTL Design Engineer
Sunil V L
Ventana Micro Systems Inc.
Principal Software Engineer
Larry Lapides
Imperas Software
Vice President Sales
TL
Tom Leahy
SiFive
Head of Aerospace and Defense Business Development
Peter Lewin
Imagination Technologies
Director of CPU Ecosystems
DL
Dingji Li
Shanghai Jiao Tong University
Senior Ph.D. Candidate
See Chin Liang
StarFive Technology
Director of Software Engineering
Yuning Liang
Xcalibyte
Founder & CEO
WL
Wei-han Lien
Tenstorrent Inc.
Fellow Machine Learning Hardware Architecture
KL
Knute Lingaard
SiFive
Principal Engineer
Mark Lippett
CEO
XMOS
Patrick Little
SiFive
Chairman, President & CEO
XM
Xiaohan Ma
Alibaba
Gordan Markus
Canonical Ltd.
Silicon Alliances Partner Manager
BM
Bill McSpadden
RISC-V International
DM
Dan Mender
Green Hills Software
VP Business Development
NG
Naresh Gangadharan Menon
Imagination Technologies
Director of Product Management, CPU
John Min
Andes Technology USA
Director of Solution Engineering
Lee Moore
Imperas Software
Senior Applications Engineer
Henk Muller
XMOS
CTO
Christoph Müllner
VRULL
Software developer and security researcher
Alastair Murray
Codeplay Software
VP Product Engineering
GR
G. Richard Newell
Microchip Technology Inc.
Associate Technical Fellow
Casey Ng
Cadence
Audio Product Marketing Director
Chris Owen
Imagination Technologies
Senior Principal Software Engineer
KP
Kolya Panchenko
SiFive
Anup Patel
Ventana Micro Systems Inc
Principal Software Engineer
Sandro Pinto
Universidade do Minho
Associate Research Professor
AR
Allison Randal
Rivos
Principal MTS
Calista Redmond
RISC-V International
CEO
DR
Dom Rizzo
Google
OpenTitan TechLead/Manager
Markku-Juhani O. Saarinen
PQShield Ltd.
Staff Cryptography Architect
Ravi Sahita
Rivos Inc.
Principal Member of Technical Staff
Kumar Sankaran
Ventana
VP SW and Solutions
PS
Pierre-Andre Saulais
Codeplay Software
Senior Principal Software Engineer
Heinrich Schuchardt
Canonical
RISC-V lead engineer
VS
Ved Shanbhogue
Rivos Inc.
Sr. Member Technical Staff
Makeljana Shkuti
VRULL
Ray Simar
Rice University
Professor in the Practice
Richard Sites
retired
retired
DS
Dan Smathers
Seagate Technology
Sr. Staff Engineer, RISC-V Design Team
John Sotiropoulos
Breker Verification Systems
Principal Applications Engineer
Charlie Su
Andes Technology
President and CTO
Aimee Sutton
Imperas Software
Director of Product Engineering
Lip-Bu Tan
Chairman, Walden International Founding Managing Partner, Celesta Capital and Walden Catalyst Ventures Executive Chairman, Cadence Design Systems, Inc.
Mike Thompson
OpenHW
OpenHW Group Director of Engineering, Verification Task Group
Philipp Tomsich
VRULL GmbH
Chief Technologist
Manju Varma
Director of Product Management
Qualcomm Technologies, Inc.
Remi van Veen
Solid Sands B.V.
Qualification Lead Engineer
Stefan Wallentowitz
Munich University of Applied Sciences
Professor
XW
Xi Wang
RIOS Lab, Tsinghua University
Postdoctoral Researcher
SW
Steve Wanless
Red Hat
Business Strategist Linux
Bruce Weyer
Microchip
Corporate Vice President, FPGA
Jennifer Winikus
University at Buffalo
Assistant Professor of Teaching
Fei Wu
Intel
System Software Architect
DX
Dongjie Xie
Tenstorrent
Staff Engineer
BY
Bicheng Yang
Shanghai Jiao Tong University
Ph.D. Candidate
KY
Kai Yick
Google
Hardware Manager
Ligang Zhang
Alibaba
Staff Engineer
