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December 13-14, 2022 | San Jose, CA + Virtual
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Tuesday, December 13 • 12:05pm - 12:25pm
High-Performance RISC-V Processor for Computation Acceleration and Server - Wei-han Lien, Tenstorrent Inc.

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Explosive computation demand in AI, AR/VR, financial computing, and computational biology has driven innovations in computation acceleration technology. Exponential model size growth coupled with the torrent of model data inputs requires a new heterogenous computation platform to integrate innovations in the software programming model, compiler, networking technology, semiconductor process, and packaging technology. Ascalon high-performance RISC-V super-scalar processor is one of the Tenstorrent technological components to address such computational demands. Ascalon processor is an 8-wide decode O-o-O machine with advanced branch predictors, large ROB, and wide instruction execution pipelines with powerful vector units. A compact and efficient cache-coherent cluster contains many cores and a large shared cache. A hierarchical coherent fabric connects Ascalon clusters to form a high-performance ccNUMA computation platform. The platform can be used as composable chiplet elements with high-performance memory sub-systems and accelerators to create domain-specific hardware with industrial-leading price-performance solutions.


Wei-han Lien

Fellow Machine Learning Hardware Architecture, Tenstorrent Inc.
Wei-han Lien is a Chief CPU Architect and Fellow in Machine Learning hardware architecture. He is currently leading an architecture team in defining a high-performance RISC-V CPU, fabric, system caching, and high-performance memory sub-system for the Tenstorrent heterogeneous high-performance... Read More →

Tuesday December 13, 2022 12:05pm - 12:25pm PST
Grand Ballroom 220 C