RISC-V Summit 2022

Since Krste Asanovic last talked about the Fast Interrupt (CLIC) Task Group at the 8th RISC-V Workshop in Barcelona 2018, a lot of RISC-V interrupt architecture development has occurred. 6 Proof-of-Concept CLIC implementations have been publicly announced, PLIC specification has been frozen, Advanced Interrupt Architecture (AIA) and APLIC supporting MSI/Hypervisor specification has been frozen. And in the 2021 Summit the AIA and APLIC was presented showing application level interrupts and resumable non-maskable interrupts (RNMI) is in development. CLIC development focus has been to improve interrupt latency and throughput and provide individual interrupt configuration flexibility primarily targeting the embedded interrupt space. This talk discusses where CLIC fits and complements other RISC-V interrupt schemes, CLIC features and benefits, interrupt handler code examples such as interrupt preemption, skipping context save/restore on back-to-back interrupts, and a status update of where CLIC is in its development and its ratification schedule.