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December 13-14, 2022 | San Jose, CA + Virtual
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Wednesday, December 14 • 3:30pm - 3:50pm
The Continuum of RISC-V Compliance and Verification Testing - Simon Davidmann, Imperas Software & Allen Baum, Esperanto Technologies, Inc.

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RISC-V International develops and maintains the RISC-V ISA specification and provides basic architectural tests to confirm if users have read the specification. OpenHW Group develops and maintains open-source RISC-V processor cores and develops a unified open source testbench and verifies the cores to industrial quality levels. Conceptually, verification ensures you have implemented what you have specified for your design, and the compliance testing ensures you have met the ISA specification. There is a continuum of testing. This talk discusses the boundary between compliance and design verification, and the different technologies and tools required for each area. Also, the new projects in OpenHW Group are introduced that are moving the RISC-V Verification open ecosystem forward in the areas of Functional Coverage, Verification Standards, and Core quality with quantitative measurement for use with both commercial and open-source projects. An example illustrates the new open standard RISC-V Verification Interface (RVVI) Virtual Verification Peripheral definitions (VVP) and use in compliance testing of privilege mode items such as asynchronous interrupts and debug mode requests.

avatar for Simon Davidmann

Simon Davidmann

CEO, Imperas Software
Simon Davidmann has been working on simulators and EDA products since 1978. He is founder and CEO of Imperas and initiator of Open Virtual Platforms (www.OVPworld.org) - the place for Fast Processor Models. Simon is also the chair of the Verification Task Group of the OpenHW Group... Read More →
avatar for Allen Baum

Allen Baum

Chair of RISC-V International Architecture Test SIG, Esperanto Technologies, Inc.
Allen Baum, Esperanto Technologies System ArchitectI have been involved in computer architecture for 50 years, including working on processors for HP (HPPA), Apple, ARM, DEC StrongArm and Alpha, and Intel Xeon processors.

Wednesday December 14, 2022 3:30pm - 3:50pm PST
Grand Ballroom 220 C
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