RISC-V Summit 2022

RISC-V Vector (RVV) extension has been proposed to achieve high-performance executions of vectorization computing. However, RVV introduces 217 new instructions, 7 new CSRs and diverse configuration parameters. Such complexity makes it difficult to produce a golden test suite for developers, especially due to the combinations of distinct RVV parameter configurations like vlen, vsew, vmul, etc. In order to address such issue, RIOS Lab cooperate with the RISC-V foundation and design a configurable RVV test generator for the RISC-V community. We first designed and implemented the RVV Sail Model as the golden model to execute the RVV instructions. With the Sail model support, we further developed a configurable test generator with quantifiable coverage for RISC-V Vector Extension. Users are able to select instructions to be tested and set configuration parameters combination, then the associative tests are automatically generated. The entire flow is compatible with the latest RISCOF infrastructures which are massively utilized by RISC-V tests. We will also demonstrate our RVV support for RISCV-ISAC and RISCOF to obtain a quantitative coverage report.