RISC-V Summit 2022

RISC-V is an open ISA that constantly evolves to address new performance needs and applications. We present an open and collaborative workflow, built on some of the core development tools (QEMU, GCC, LLVM) maintained by the RISC-V community, that shapes the evolution of the RISC-V ISA using quantitive and qualitative analysis of benchmarks and application workloads—aimed to stay ahead of evolving application requirements and beat those benchmarks. These analysis techniques used are demonstrated based on EEMBC CoreMark, the floating-point workloads of SPEC CPU 2017, and ECMAScript. Some of the more surprising results of this workflow are already becoming part of future RISC-V extensions or are integrated into our software ecosystem: novel compiler optimizations, better utilization of existing extensions, and new instructions ranging from the conditional operations of XVentanaCondOps to new floating-point instructions form the basis for RISC-V gaining a performance lead over competing architectures.