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December 13-14, 2022 | San Jose, CA + Virtual
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Wednesday, December 14 • 1:50pm - 2:10pm
RISC-V Perf-Model: An Open Source Cycle Accurate Performance Model for Community-wide use - Knute Lingaard, SiFive & Arup Chakraborty, Ventana Microsystems

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RISC-V Performance Modeling SIG, as per its charter, drives development of open-source cycle-accurate performance models of example processor microarchitectures, for use and exploration by the RISC-V community. In this talk, we will introduce Sparta, an event driven framework for micro-architectural simulation and its relevant semantics. Next, we will introduce an end-to-end flow of an instruction trace driven configurable performance model of an example out-of-order processor, built using Sparta framework including a quick demonstration. We will further talk about our near term plan of enhancement of the model, including a list of microarchitectural features for the modeled example processor. We will end by showcasing an associated visualization tool, Helios, that consumes cycle-based performance data generated by running the model and can be used for performance analysis and debugging


Knute Lingaard

Principal Engineer, SiFive
Knute Lingaard is a Principal Engineer skilled in performance/functional modeling, software design, C++, and Python. He is the lead designer and developer of the open source GitHub project Sparcians (https://github.com/sparcians): a C++/Python project providing discrete event-driven... Read More →

Arup Chakraborty

Sr. Staff Engineer, Ventana Microsystems
18 years of experience in performance analysis, performance modeling, benchmarking, embedded software development. Have worked in multiple organizations (STMicroelectronics, Freescale / NXP, Samsung and currently, in Ventana Microsystems) in various roles doing development of C/C... Read More →

Wednesday December 14, 2022 1:50pm - 2:10pm PST
Grand Ballroom 220 A
  Technical, Software