RISC-V Summit 2022

RISC-V Performance Modeling SIG, as per its charter, drives development of open-source cycle-accurate performance models of example processor microarchitectures, for use and exploration by the RISC-V community. In this talk, we will introduce Sparta, an event driven framework for micro-architectural simulation and its relevant semantics. Next, we will introduce an end-to-end flow of an instruction trace driven configurable performance model of an example out-of-order processor, built using Sparta framework including a quick demonstration. We will further talk about our near term plan of enhancement of the model, including a list of microarchitectural features for the modeled example processor. We will end by showcasing an associated visualization tool, Helios, that consumes cycle-based performance data generated by running the model and can be used for performance analysis and debugging