RISC-V Summit 2022

Technology trends are mandating software/hardware co-design for HPC systems. An Open Standard Instruction Set Architecture (ISA) like RISC-V enables a powerful co-design paradigm. Presently, RISC-V lacks the maturity of other closed ISAs available on the market and many in the HPC community are unfamiliar with the details of RISC-V and/or incorrectly associate the ISA and development efforts as being limited to the embedded community. However, today, there is a focused and dedicated effort underway within the RISC-V community (well-funded companies, government support, and research) to bring RISC-V into the HPC space. As part of this presentation, we will update the larger community on our efforts (identify the HPC gaps, provide standardized ISA solutions and lead the effort to build up the ecosystem) as well as solicit feedback for prioritization of next steps. We will present the status of the current SW and HW RISC-V ecosystem with a focus on HPC. This is a call to action to address the gaps andprioritize efforts that target HPC with RISC-V hardware and the associated software stack.