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Thursday, December 15 • 10:30am - 11:25am
Tutorial: Choosing Appropriate Verification Techniques for Desired RISC-V Processor Quality - Aimee Sutton & Lee Moore, Imperas Software

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As experienced SoC design verification (DV) teams take up the RISC-V processor verification challenge new approaches and techniques are required over traditional top-down block level testing. RISC-V verification plans need to address the full complexity of RISC-V features including Vector extensions, PMP security, multi-hart, multi-issue plus other advanced features. Coverage metrics have been the traditional approach to ensure a design is ready for release to prototype manufacture. For a complete RISC-V verification plan, coverage analysis needs to include all the complexities of the privilege specification including processor modes and asynchronous events. This tutorial presents a structured approach to RISC-V processor verification. It covers the basic steps from setting up an initial verification environment (testbench) to using the latest open standards for VIP (Verification IP) and the resources available within the RISC-V verification ecosystem. It highlights the importance of a verification plan and metric-driven verification for RISC-V processor designs that are destined for silicon production.


Aimee Sutton

Director of Product Engineering, Imperas Software
Aimee Sutton is Director of Product Engineering at Imperas Software
avatar for Lee Moore

Lee Moore

Senior Applications Engineer, Imperas Software
Lee Moore is the lead engineer at Imperas for RISC-V processor models and simulation tools. Prior to Imperas, Lee worked as a senior consulting engineer for EDA vendors such as Co-Design Automation and Ambit, and for ASIC vendor NEC Electronics. Lee is also a private pilot, and recently... Read More →

Thursday December 15, 2022 10:30am - 11:25am PST
Grand Ballroom 220 C
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