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December 13-14, 2022 | San Jose, CA + Virtual
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Tuesday, December 13 • 4:20pm - 4:40pm
The New Verification Ecosystem that Supports RISC-V Verification for all Adopters - Lee Moore, Imperas Software & John Sotiropoulos, Breker Verification Systems

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The RISC-V design freedoms have enabled implementers to innovate new and creative solutions. As a design progresses from concept to completion, the flexibility of RISC-V has implications for the hardware functional verification teams. This talk covers the latest developments in the RISC-V verification ecosystem to address new approaches for processor verification. These include: open standards to support universal testbenches and VIP (Verification IP) reuse, coverage libraries and quantitative measures for test infrastructure quality, and novel techniques to verify cache coherency and SoC integration. Based on examples from several popular open-source cores this talk will provide guidelines that can help both open-source and commercial projects address the RISC-V functional verification challenge.

Speakers
avatar for John Sotiropoulos

John Sotiropoulos

Principal Applications Engineer, Breker Verification Systems
John is a Principal Applications Engineer with Breker Verification Systems, working on Test Suite Synthesis and Portable Stimulus solutions. John has extensive verification experience in senior engineering roles at companies such as Intel, Facebook and Draper Labs. He also worked... Read More →
avatar for Lee Moore

Lee Moore

Senior Applications Engineer, Imperas Software
Lee Moore is the lead engineer at Imperas for RISC-V processor models and simulation tools. Prior to Imperas, Lee worked as a senior consulting engineer for EDA vendors such as Co-Design Automation and Ambit, and for ASIC vendor NEC Electronics. Lee is also a private pilot, and recently... Read More →


Tuesday December 13, 2022 4:20pm - 4:40pm PST
Grand Ballroom 220 C
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