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December 13-14, 2022 | San Jose, CA + Virtual
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Tuesday, December 13 • 2:40pm - 3:00pm
The RISC-V Vector Cryptography Extensions - G. Richard Newell, Microchip Technology Inc. & Ken Dockser, Rivos Inc.

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In 2021 the lightweight Scalar Cryptography and Entropy Source extensions were ratified, aimed at RV32 and RV64 CPUs. This year the Vector Cryptography Extensions will be finished. These include Vector ISA extensions for efficiently performing AES, GHASH, SHA2, SM3, and SM4 cryptographic calculations using the large registers made available by the Vector Extension, mainly targeting higher-end systems like personal computers and servers, though they will also run efficiently on smaller vector machines with 128-bit or longer vector registers. These extensions include some vector bit-manipulation instructions that help optimize kernels based on the cryptographic instructions as well as supporting other algorithms such as prime- and binary-field ECC and SHA3, which is important for post-quantum cryptography. This talk reviews the Vector Cryptographic Extensions, the rationale behind them, and how they are used to efficiently implement cryptographic kernels.


G. Richard Newell

Associate Technical Fellow, Microchip Technology Inc.
Richard Newell is responsible for architecting the security features for Microchip's current and future generations of FPGAs and SoC FPGAs. Richard has an electrical engineering background with over 45 years of experience in analog and digital signal processing, cryptography, control... Read More →
avatar for Ken Dockser

Ken Dockser

CPU Architect, Rivos Inc.
Ken Dockser is a CPU architect at Rivos Inc, where he defines the macro-architecture for high-performance RISC-V CPUs. Ken's previous position was at Qualcomm where he headed up Processor Research (concentrating on RISC-V) as a Senior Director. Before that he was a CPU architect for... Read More →

Tuesday December 13, 2022 2:40pm - 3:00pm PST
Grand Ballroom 220 A
  Technical, ISA