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RISC-V Summit 2022 has ended
December 13-14, 2022 | San Jose, CA + Virtual
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Monday, December 12
 

8:00am PST

Registration
Monday December 12, 2022 8:00am - 5:00pm PST
Hall 2 Foyer
  Registration

9:00am PST

Member Day Session: J Extension Group Meeting
Must be a RISC-V Member in order to attend these sessions. For any questions, please contact events@linuxfoundation.org. 
Monday December 12, 2022 9:00am - 9:25am PST
Grand Ballroom 220 C
  Member Day Sessions

9:30am PST

RISC-V FutureWatch - Imperas: The 360 Ecosystem of RISC-V - Simon Davidmann, CEO at Imperas Software and Verification Task Group Chair at OpenHW Group
The 360 Ecosystem of RISC-V.

The most important announcements of the year happen at the RISC-V Global Summit. Now, RISC-V FutureWatch collects them all in one place. From 9am to 5pm, this invite-only series of presentations helps press, analysts, influencers, consultants, and other opinion leaders identify the stories that are driving RISC-V’s success. Product launches, roadmap introductions, calls to action for the global RISC-V community – it’s all here.
Monday December 12, 2022 9:30am - 9:55am PST
Grand Ballroom 220 A
  FutureWatch Sessions

9:30am PST

Member Day Session: AP-TEE Group Meeting
Must be a RISC-V Member in order to attend these sessions. For any questions, please contact events@linuxfoundation.org. 
Monday December 12, 2022 9:30am - 9:55am PST
Grand Ballroom 220 C
  Member Day Sessions

9:30am PST

Member Day Session: Developer Boards
Must be a RISC-V Member in order to attend these sessions. For any questions, please contact events@linuxfoundation.org. 
Monday December 12, 2022 9:30am - 9:55am PST
Grand Ballroom 220 B
  Member Day Sessions

10:00am PST

RISC-V FutureWatch - Ventana: Balaji Baktha, Founder and CEO, Ventana
The most important announcements of the year happen at the RISC-V Global Summit. Now, RISC-V FutureWatch collects them all in one place. From 9am to 5pm, this invite-only series of presentations helps press, analysts, influencers, consultants, and other opinion leaders identify the stories that are driving RISC-V’s success. Product launches, roadmap introductions, calls to action for the global RISC-V community – it’s all here.
Monday December 12, 2022 10:00am - 10:25am PST
Grand Ballroom 220 A
  FutureWatch Sessions

10:00am PST

Member Day Session: Development Partners & Labs
Must be a RISC-V Member in order to attend these sessions. For any questions, please contact events@linuxfoundation.org. 
Monday December 12, 2022 10:00am - 10:25am PST
Grand Ballroom 220 B
  Member Day Sessions

10:00am PST

Member Day Session: HPC Group Meeting
Must be a RISC-V Member in order to attend these sessions. For any questions, please contact events@linuxfoundation.org. 
Monday December 12, 2022 10:00am - 10:25am PST
Grand Ballroom 220 C
  Member Day Sessions

10:30am PST

Morning Break
Breakfast Muffins - Bran, Blueberry, Chocolate
Yogurts - Berry, Peach, Plain w/ Granola
Seasonal Sliced Fruit, Melon, Berries
Monday December 12, 2022 10:30am - 11:00am PST
Grand Ballroom Foyer
  Breaks + Event Experiences

11:00am PST

RISC-V FutureWatch - Andes Technology: Expanding the RISC-V Horizon and Beyond - Frankwell Lin, Chairman and CEO & Charlie Su, President and CTO, Andes Technology
The most important announcements of the year happen at the RISC-V Global Summit. Now, RISC-V FutureWatch collects them all in one place. From 9am to 5pm, this invite-only series of presentations helps press, analysts, influencers, consultants, and other opinion leaders identify the stories that are driving RISC-V’s success. Product launches, roadmap introductions, calls to action for the global RISC-V community – it’s all here.
Monday December 12, 2022 11:00am - 11:25am PST
Grand Ballroom 220 A
  FutureWatch Sessions

11:00am PST

Member Day Session: OS-A SEE Group Meeting
Must be a RISC-V Member in order to attend these sessions. For any questions, please contact events@linuxfoundation.org. 
Monday December 12, 2022 11:00am - 11:25am PST
Grand Ballroom 220 C
  Member Day Sessions

11:00am PST

Member Day Session: Ambassadors
Must be a RISC-V Member in order to attend these sessions. For any questions, please contact events@linuxfoundation.org. 
Monday December 12, 2022 11:00am - 11:55am PST
Grand Ballroom 220 B
  Member Day Sessions

11:30am PST

RISC-V FutureWatch - SiFive: Introducing the Horse Creek Development Board - Jack Kang, SVP, Biz Dev, CX, Corp Marketing, SiFive
Jack Kang will talk more about this exciting collaboration between Intel and SiFive on the Horse Creek development board.

The most important announcements of the year happen at the RISC-V Global Summit. Now, RISC-V FutureWatch collects them all in one place. From 9am to 5pm, this invite-only series of presentations helps press, analysts, influencers, consultants, and other opinion leaders identify the stories that are driving RISC-V’s success. Product launches, roadmap introductions, calls to action for the global RISC-V community – it’s all here.
Monday December 12, 2022 11:30am - 11:55am PST
Grand Ballroom 220 A
  FutureWatch Sessions

11:30am PST

Member Day Session: SoC Infra Group Meeting
Must be a RISC-V Member in order to attend these sessions. For any questions, please contact events@linuxfoundation.org. 
Monday December 12, 2022 11:30am - 11:55am PST
Grand Ballroom 220 C
  Member Day Sessions

12:00pm PST

Member Day Session: Academic
Must be a RISC-V Member in order to attend these sessions. For any questions, please contact events@linuxfoundation.org. 
Monday December 12, 2022 12:00pm - 12:25pm PST
Grand Ballroom 220 B
  Member Day Sessions

12:00pm PST

Member Day Session: ISA Infra Group Meeting
Must be a RISC-V Member in order to attend these sessions. For any questions, please contact events@linuxfoundation.org. 
Monday December 12, 2022 12:00pm - 12:25pm PST
Grand Ballroom 220 C
  Member Day Sessions

12:25pm PST

Lunch Break
The Lunch Box 
  • Banh Mi (V/DF) - Herb Roasted Tofu, Cucumber, Pickled Daikon, Carrots, Cilantro, Chili Aioli, French Hero
  • So California Sandwich (DF) - Smoked Turkey, Maple Bacon, Garlic Aioli, Arugula, Whole Wheat Multigrain Roll
  • Romaine Salad (Vegan/GF/DF) - Turnips, Lentils, Cranberries, Apple Cider Vinaigrette
Kettle Chips (Vegan/GF/DF)
Potato Salad (V/GF/DF)
Chocolate Chip Cookie (V)
Brownie (Vegan)
Monday December 12, 2022 12:25pm - 1:30pm PST
Lower Level Foyer
  Breaks + Event Experiences

1:30pm PST

RISC-V FutureWatch: Introducing a New Software-defined Silicon Capability to the RISC-V Community - Mark Lippett, XMOS
The most important announcements of the year happen at the RISC-V Global Summit. Now, RISC-V FutureWatch collects them all in one place. From 9am to 5pm, this invite-only series of presentations helps press, analysts, influencers, consultants, and other opinion leaders identify the stories that are driving RISC-V’s success. Product launches, roadmap introductions, calls to action for the global RISC-V community – it’s all here.
Speakers
avatar for Mark Lippett

Mark Lippett

XMOS, CEO
Mark started with XMOS in 2008 in the role of VP Engineering, before being appointed as COO and taking the helm as CEO in 2016. Mark has extensive experience across the electronics industry, with involvement in both blue-chip and start-up companies.Prior to XMOS Mark was founder and... Read More →

XMOS RISC V FutureWatch pdf
Monday December 12, 2022 1:30pm - 1:55pm PST
Grand Ballroom 220 A
  FutureWatch Sessions
  • Slides Attached Yes

1:30pm PST

Member Day Session: Priv Software Group Meeting
Must be a RISC-V Member in order to attend these sessions. For any questions, please contact events@linuxfoundation.org. 
Monday December 12, 2022 1:30pm - 1:55pm PST
Grand Ballroom 220 C
  Member Day Sessions

1:30pm PST

Member Day Session: Marketing Committee
Must be a RISC-V Member in order to attend these sessions. For any questions, please contact events@linuxfoundation.org. 
Monday December 12, 2022 1:30pm - 2:25pm PST
Grand Ballroom 220 B
  Member Day Sessions

2:00pm PST

RISC-V FutureWatch: MIPS - Bringing a New Level of Scalability to RISC-V - MIPS eVocore P8700 Now Available - Itai Yaromm, VP, Sales & Marketing, MIPS Tech
Autonomous driving cars and other complex applications require heterogeneous processing, security and scalability. MIPS is leading the way in RISC-V and pushing the limits on performance with its eVocore P8700.

The most important announcements of the year happen at the RISC-V Global Summit. Now, RISC-V FutureWatch collects them all in one place. From 9am to 5pm, this invite-only series of presentations helps press, analysts, influencers, consultants, and other opinion leaders identify the stories that are driving RISC-V’s success. Product launches, roadmap introductions, calls to action for the global RISC-V community – it’s all here.
Monday December 12, 2022 2:00pm - 2:25pm PST
Grand Ballroom 220 A
  FutureWatch Sessions

2:00pm PST

Member Day Session: Apps & Tools Group Meeting
Must be a RISC-V Member in order to attend these sessions. For any questions, please contact events@linuxfoundation.org. 
Monday December 12, 2022 2:00pm - 2:25pm PST
Grand Ballroom 220 C
  Member Day Sessions

2:30pm PST

Member Day Session: Events and Content Committee
Must be a RISC-V Member in order to attend these sessions. For any questions, please contact events@linuxfoundation.org. 
Monday December 12, 2022 2:30pm - 2:55pm PST
Grand Ballroom 220 B
  Member Day Sessions

2:30pm PST

Member Day Session: Priv ISA Group Meeting
Must be a RISC-V Member in order to attend these sessions. For any questions, please contact events@linuxfoundation.org. 
Monday December 12, 2022 2:30pm - 2:55pm PST
Grand Ballroom 220 C
  Member Day Sessions

3:00pm PST

RISC-V FutureWatch - Microchip: RISC-V based Mid-range FPGAs: Fueling The Edge Compute Revolution - Shakeel Peera, Vice President, Marketing and Strategy, Microchip
Mid-range FPGAs and System-on-Chip (SoC) FPGAs have played a major role in moving computer workloads to the network edge. Microchip Technology has helped fuel this transition with its award-winning FPGAs while also delivering the first RISC-V-based FPGAs that provide twice the power efficiency of competing mid-range FPGAs and feature a best-in-class design, operating system and solutions ecosystem. Microchip will be showcasing its existing solutions and previewing its forthcoming portfolio, inclusive of new platforms for edge and space compute.


The most important announcements of the year happen at the RISC-V Global Summit. Now, RISC-V FutureWatch collects them all in one place. From 9am to 5pm, this invite-only series of presentations helps press, analysts, influencers, consultants, and other opinion leaders identify the stories that are driving RISC-V’s success. Product launches, roadmap introductions, calls to action for the global RISC-V community – it’s all here.
Monday December 12, 2022 3:00pm - 3:25pm PST
Grand Ballroom 220 A
  FutureWatch Sessions

3:00pm PST

Member Day Session: Market Development Committee
Must be a RISC-V Member in order to attend these sessions. For any questions, please contact events@linuxfoundation.org. 
Monday December 12, 2022 3:00pm - 3:25pm PST
Grand Ballroom 220 B
  Member Day Sessions

3:00pm PST

Member Day Session: Unpriv ISA Group Meeting
Must be a RISC-V Member in order to attend these sessions. For any questions, please contact events@linuxfoundation.org. 
Monday December 12, 2022 3:00pm - 3:25pm PST
Grand Ballroom 220 C
  Member Day Sessions

3:30pm PST

Afternoon Break
Dessert Bars - Raspberry, Lemon
Individual Kettle Style Chips - Sea Salt, BBQ or Spicy
Crudité of Seasonal Vegetables, Holland Red Gouda, Fruit Chutneys, Crackers, Red Pepper Hummus
Monday December 12, 2022 3:30pm - 3:55pm PST
Grand Ballroom Foyer
  Breaks + Event Experiences

4:00pm PST

RISC-V General Membership Meeting (Open to all RISC-V Members)
Open to all RISC-V Members. 
Speakers
avatar for Mark Himelstein

Mark Himelstein

CTO, RISC-V International
Mark Himelstein is the CTO for RISC-V International. Before RISC-V international Mark Himelstein was the President of Heavenstone, Inc. which concentrated on Strategic, Management, and Technology Consulting providing product architecture, analysis, mentoring and interim management... Read More →

mark's general meeting talk pdf
Monday December 12, 2022 4:00pm - 5:30pm PST
Grand Ballroom 220 A
  Member Day Sessions
  • Slides Attached Yes

5:30pm PST

RISC-V Summit Kickoff Party - Hosted by Imperas
Imperas RISC-V Summit KickOff Party
Come celebrate the start of RISC-V Summit at the Imperas RISC-V Summit Kickoff Party! All RISC-V members and Summit attendees are welcome to join for food, drinks, and networking.

Monday December 12, 2022 5:30pm - 7:00pm PST
Concourse Level
  Breaks + Event Experiences
 
Tuesday, December 13
 

7:30am PST

Registration
Tuesday December 13, 2022 7:30am - 6:00pm PST
Hall 2 Foyer
  Registration

9:00am PST

Keynote: Welcome & Opening Remarks - Calista Redmond, CEO, RISC-V International
Speakers
avatar for Calista Redmond

Calista Redmond

CEO, RISC-V International
Calista Redmond is the CEO of RISC-V International with a mission to expand and engage RISC-V stakeholders, compel industry adoption, and increase visibility and opportunity for RISC-V within and beyond RISC-V International. Prior to RISC-V International, Calista held a variety of... Read More →

Tuesday December 13, 2022 9:00am - 9:15am PST
Hall 3
  Keynote Sessions

9:20am PST

Keynote: Accelerating Innovation with RISC-V: Past, Present and Future - Manju Varma, Director of Product Management, Qualcomm Technologies, Inc.
Speakers
avatar for Manju Varma

Manju Varma

Qualcomm Technologies, Inc., Director of Product Management
Manju Varma is currently the Director of Product Management at Qualcomm Technologies. She leads CPU Technology Product Management at Qualcomm. Her role encompasses driving CPU strategy and Roadmap across Qualcomm’s portfolio of products with applications in Mobile, Automotive, AR/MR/VR... Read More →

Tuesday December 13, 2022 9:20am - 9:40am PST
Hall 3
  Keynote Sessions

9:40am PST

Keynote: RISC-V Challenges & Opportunities - Lip-Bu Tan, Founder and Chairman, Walden International; Founding Managing Partner of Celesta Capital & Walden Catalyst Ventures; Executive Chairman, Cadence Design Systems, Inc.
Speakers
avatar for Lip-Bu Tan

Lip-Bu Tan

Chairman, Walden International Founding Managing Partner, Celesta Capital and Walden Catalyst Ventures Executive Chairman, Cadence Design Systems, Inc.
Lip-Bu Tan is Founder and Chairman of Walden International (“WI”), a leading venture capital firm managing cumulative capital commitments of greater than $4 billion; and Founding Managing Partner of Celesta Capital and Walden Catalyst Ventures, a venture capital firm focused on... Read More →

3. Lip Bu Tan FINAL pdf
Tuesday December 13, 2022 9:40am - 10:00am PST
Hall 3
  Keynote Sessions
  • Slides Attached Yes

10:00am PST

RISC-V Spotlight: Improving RISC-V Quality with Verification Standards and Advanced Methodologies - Simon Davidmann, CEO, Imperas Software & Verification Task Group Chair, OpenHW Group
The freedom of RISC-V represents both new innovations in design and also the migration of
verification responsibility. This keynote highlights the challenges facing SoC teams as they
adopt RISC-V and provides a perspective on how the use of new verification standards and
methodologies drives down cost, quality risk, and development time.
Speakers
avatar for Simon Davidmann

Simon Davidmann

CEO, Imperas Software
Simon Davidmann has been working on simulators and EDA products since 1978. He is founder and CEO of Imperas and initiator of Open Virtual Platforms (www.OVPworld.org) - the place for Fast Processor Models. Simon is also the chair of the Verification Task Group of the OpenHW Group... Read More →

Imperas RISC V Summit 2022 Keynote Davidmann.FINAL pdf
Tuesday December 13, 2022 10:00am - 10:15am PST
Hall 3
  Keynote Sessions
  • Slides Attached Yes

10:15am PST

RISC-V Spotlight: Ventana Brings RISC-V to Data Center with Veyron V1 - Balaji Baktha, Founder, President, CEO and Chairman, Ventana Micro Systems
Speakers
avatar for Balaji Baktha

Balaji Baktha

President & CEO, Ventana Micro Systems
Balaji Baktha is the founder, chairman and CEO of Ventana Micro Systems. He is an experienced semiconductor executive and serial technology entrepreneur and investor. Previously, Balaji founded Veloce Technologies, the world’s first 64-bit ARM based high performance processor. Prior... Read More →

Tuesday December 13, 2022 10:15am - 10:30am PST
Hall 3
  Keynote Sessions

10:35am PST

RISC-V Spotlight: Delivering on Real-World Customer Challenges - Patrick Little, Chairman, President & CEO, SiFive
Patrick will talk about how the momentum and excitement for RISC-V is growing, and the importance of a continued focus on building a strong community and ecosystem, which is critical to its success. With customer examples, he’ll show how RISC-V is winning by addressing unmet or poorly met needs and by offering longevity and flexibility.
Speakers
avatar for Patrick Little

Patrick Little

Chairman, President & CEO, SiFive
Patrick is Chairman, President, and CEO of SiFive. As a business leader and technologist, he has led SiFive’s accelerated expansion into high performance RISC-V computing platforms. Previously, he was Senior Vice President & General Manager at Qualcomm, where he led their successful... Read More →

Tuesday December 13, 2022 10:35am - 10:50am PST
Hall 3
  Keynote Sessions

10:50am PST

RISC-V Spotlight: Avoiding Murphy's Law and Satan's Law Without Selling your Soul - Ron Black, CEO, Codasip
No one knows Murphy’s Law of "anything that can go wrong will go wrong" better than automotive OEMs who always must assume this to be true and create systems with safety in mind for any and all risks of system failure. But with connected cars, there is a new law to consider: Satan’s Law. As an automotive manufacturer, you must now also assume all people are bad and want to hack your system. Much is to gain by adopting an integrated approach that can provide a complimentary safety and security solution that is scalable in either direction while balancing PPA.
Speakers
avatar for Ron Black

Ron Black

CEO, Codasip
Dr. Black has over 30 years of industry experience. Before joining Codasip, he has been President and CEO at Imagination Technologies and previously CEO at Rambus, MobiWire, UPEK, and Wavecom. He holds a BS and MS in Engineering and a Ph.D. in Materials science from Cornell University... Read More →

7. Ron Black pdf
Tuesday December 13, 2022 10:50am - 11:00am PST
Hall 3
  Keynote Sessions
  • Slides Attached Yes

11:00am PST

RISC-V Spotlight: How RISC-V Speeds the Journey of Innovation - Bruce Weyer, Corporate Vice President, FPGA, Microchip
As an expert in the RISC-V ISA, Bruce will describe how RISC-V and Microchip FPGAs are a perfect pairing of innovation that delivers power-efficient edge compute solutions for ground-based as well as space applications. Learn how RISC-V makes anything possible as the industry evolves from embedded to edge computing.
Speakers
avatar for Bruce Weyer

Bruce Weyer

Corporate Vice President, FPGA, Microchip
Bruce Weyer is a semiconductor industry veteran with over 35 years of experience. He joined Microchip Technology in 2014 and currently leads the company’s FPGA business unit, where he is responsible for the unit’s operational execution, strategy and growth. Bruce has held leadership... Read More →

8. Bruce Weyer pdf
Tuesday December 13, 2022 11:00am - 11:10am PST
Hall 3
  Keynote Sessions
  • Slides Attached Yes

11:10am PST

Morning Break
Old Fashioned Donuts - Maple, Chocolate, Glazed
Donuts (Vegan)- Apple Cinnamon
Kale, Cucumber, Yogurt Smoothie (V/GF)
Banana, Mango, Turmeric, Oat Milk Smoothie (Vegan/GF/DF)
Tuesday December 13, 2022 11:10am - 11:40am PST
Expo Hall - Hall 2
  Breaks + Event Experiences

11:10am PST

Expo Hall
Tuesday December 13, 2022 11:10am - 7:00pm PST
Expo Hall - Hall 2
  Breaks + Event Experiences

11:30am PST

Demo: Facilitating Trusted Application Migration to RISC-V - Xiaoxia Cui, Alibaba
This proposal introduces the Xuantie security system for Xuantie RISC-V based processors. It uses OPTEE as the security OS which is compatibility with Arm software system. It enhances the system security through security technology that is coupled with RISC-V architecture. The Xuantie security software stack follows Global Platform TEE security standard. Xuantie security system also eliminates the platform difference between Arm and RISC-V, developers can migrate trusted application from Arm to RISC-V easily.
Speakers
avatar for Xiaoxia Cui

Xiaoxia Cui

IoT Security Expert, Alibaba
Vincent Cui has been worked in embedded software industry for more than 10+ years. He is currently focusing on the IoT system software platform, that expands to specific domains such as wireless connection (BLE and WiFi), intelligent voice, graphics, multimedia and AI. He is the Vice-Chair... Read More →

Tuesday December 13, 2022 11:30am - 11:40am PST
Expo Hall - Hall 2 - Demo Theater
  Demo Theater

11:40am PST

Building a Global CORE-V Cores Ecosystem - Mike Thompson, OpenHW Group
OpenHW Group's CORE-V suite of fully open-source RISC-V cores and enabling IP and software continues to expand. From small and light embedded cores to multi-processor linux-class processor clusters, OpenHW community-driven roadmap forms a comprehensive global ecosystem.
Speakers
avatar for Mike Thompson

Mike Thompson

OpenHW Group Director of Engineering, Verification Task Group, OpenHW
Mike Thompson a senior IC functional verification engineering manager who has lead both large and small teams in all aspects of the discipline including simulation, emulation, prototyping and formal verification.  He has both hands-on and management level experience with multiple... Read More →

OpenHW Group Dec2022 pdf
Tuesday December 13, 2022 11:40am - 12:00pm PST
Grand Ballroom 220 B
  Industry

11:40am PST

SERV: 32-bit is the New 8-bit - Olof Kindgren, Qamcom
RISC-V is going places. From cars to space to data centers. But what about the billions of cores in more mundane applications such as greeting cards, toys or keyboards? This is an area traditionally served by 8-bit CPUs, but not for much longer. The award-winning SERV, the world's smallest RISC-V CPU is small enough to take on the 8-bit market while offering all the convenience of the modern RISC-V ecosystem, such as running the Zephyr RTOS. This presentation takes a look at what makes SERV so small, what it can do, how and where it is used today along with a proposed new ISA extension to further improve the applicability of RISC-V within deeply embedded systems.
Speakers
avatar for Olof Kindgren

Olof Kindgren

Senior Digital Design Engineer, Qamcom
The award-winning Olof Kindgren is a senior digital design engineer working for Qamcom. He became actively involved with free and open source silicon through the OpenRISC project in 2011 and has since then worked on many FOSSi projects with a special interest in tools and collaborations... Read More →

serv rvsummit pdf
Tuesday December 13, 2022 11:40am - 12:00pm PST
Grand Ballroom 220 C
  Industry, Edge & IoT

11:40am PST

The Road Ahead - Mark Himelstein, RISC-V International
Speakers
avatar for Mark Himelstein

Mark Himelstein

CTO, RISC-V International
Mark Himelstein is the CTO for RISC-V International. Before RISC-V international Mark Himelstein was the President of Heavenstone, Inc. which concentrated on Strategic, Management, and Technology Consulting providing product architecture, analysis, mentoring and interim management... Read More →

the road ahead (1) pdf
Tuesday December 13, 2022 11:40am - 12:00pm PST
Grand Ballroom 220 A
  Technical, ISA

12:05pm PST

High-Performance RISC-V Processor for Computation Acceleration and Server - Wei-han Lien, Tenstorrent Inc.
Explosive computation demand in AI, AR/VR, financial computing, and computational biology has driven innovations in computation acceleration technology. Exponential model size growth coupled with the torrent of model data inputs requires a new heterogenous computation platform to integrate innovations in the software programming model, compiler, networking technology, semiconductor process, and packaging technology. Ascalon high-performance RISC-V super-scalar processor is one of the Tenstorrent technological components to address such computational demands. Ascalon processor is an 8-wide decode O-o-O machine with advanced branch predictors, large ROB, and wide instruction execution pipelines with powerful vector units. A compact and efficient cache-coherent cluster contains many cores and a large shared cache. A hierarchical coherent fabric connects Ascalon clusters to form a high-performance ccNUMA computation platform. The platform can be used as composable chiplet elements with high-performance memory sub-systems and accelerators to create domain-specific hardware with industrial-leading price-performance solutions.
Speakers
WL

Wei-han Lien

Fellow Machine Learning Hardware Architecture, Tenstorrent Inc.
Wei-han Lien is a Chief CPU Architect and Fellow in Machine Learning hardware architecture. He is currently leading an architecture team in defining a high-performance RISC-V CPU, fabric, system caching, and high-performance memory sub-system for the Tenstorrent heterogeneous high-performance... Read More →

Tuesday December 13, 2022 12:05pm - 12:25pm PST
Grand Ballroom 220 C
  Industry, High-Performance Computing & Data Centers

12:05pm PST

Qualification of the C and C++ Standard Libraries for Safety-critical Applications - Remi van Veen, Solid Sands B.V.
We will explain the process used to qualify the C and C++ standard libraries for safety-critical applications. It is based on the ISO 26262 automotive Functional Safety standard. It can be used for the qualification of in-house, third-party, and open-source libraries. Qualification needs a requirements-based test suite that shows the link between the library specifications (from the ISO standards for C and C++) and tests. To translate the specification into requirements is a significant effort. We will show examples of how to extract requirements from the library specification. The next step is to define test specifications. Where the requirement defines what must be tested, the test specification describes how that is done, and guides the definition of the test itself. Coverage analysis (MC/DC) is required for ASIL D. It demonstrates completeness of the test suite. There are good tools for code coverage analysis of C code. For C++, additional care is needed because of template code in the headers, which is evaluated at compile time only. In the presentation, we will show you what we have learned from creating SuperGuard, a requirements-based test suite for C.
Speakers
avatar for Remi van Veen

Remi van Veen

Qualification Lead Engineer, Solid Sands B.V.
Remi van Veen is Qualification Lead Engineer at Solid Sands. He joined Solid Sands in 2018 to productize his research on compiler optimizations into the SuperTest compiler optimization test suite. Today his main focus is on leading compiler and library qualification projects for functional... Read More →

slides pdf
Tuesday December 13, 2022 12:05pm - 12:25pm PST
Grand Ballroom 220 B
  Industry, Automotive

12:05pm PST

RISC-V Readiness for Datacenter Deployments - Balaji Baktha, Ventana Micro Systems & Mark Himelstein, RISC-V International
In this session, we will discuss the RISC-V ecosystem as it applies to the software stack and its suitability for datacenter deployments. The session will cover key applications used in the datacenter in areas such as storage and networking.  We will also discuss how RISC-V and domain specific optimization is uniquely positioned to be the better choice to achieve the efficiency requirements for these types of data center applications.
Speakers
avatar for Balaji Baktha

Balaji Baktha

President & CEO, Ventana Micro Systems
Balaji Baktha is the founder, chairman and CEO of Ventana Micro Systems. He is an experienced semiconductor executive and serial technology entrepreneur and investor. Previously, Balaji founded Veloce Technologies, the world’s first 64-bit ARM based high performance processor. Prior... Read More →
avatar for Mark Himelstein

Mark Himelstein

CTO, RISC-V International
Mark Himelstein is the CTO for RISC-V International. Before RISC-V international Mark Himelstein was the President of Heavenstone, Inc. which concentrated on Strategic, Management, and Technology Consulting providing product architecture, analysis, mentoring and interim management... Read More →

Tuesday December 13, 2022 12:05pm - 12:25pm PST
Hall 3
  Industry, Building a Software Ecosystem

12:05pm PST

RISC-V Profiles and Profile Roadmap - Krste Asanovic, Chair, RISC-V International
This talk will describe the structure of RISC-V Profiles and the contents of the initial set of profiles: RVI20, RVA20, RVA22, and RVA23.
Speakers
avatar for Krste Asanovic

Krste Asanovic

Chair, RISC-V International
Krste Asanović is a Professor in the EECS Department at the University of California, Berkeley. He received a PhD in Computer Science from UC Berkeley in 1998 then joined the faculty at MIT, receiving tenure in 2005. He returned to join the faculty at Berkeley in 2007, where he co-founded... Read More →

Tuesday December 13, 2022 12:05pm - 12:25pm PST
Grand Ballroom 220 A
  Technical, ISA

12:30pm PST

Proving RISC-V Security Model Compliance with SESIP - Eve Atallah, NXP Semiconductors
This presentation introduces the Security Evaluation Standard for IoT Platform (SESIP) methodology, main principles and benefits, and shows how it supports efficient compliance assessment of RISC-V platforms to the security requirements of the RISC-V Platform Security Model, and how the produced results can be reused for compliance demonstration to further standards at SoC or device level, optimizing the efforts. SESIP is indeed a methodology for assessment of correct and robust implementation of security requirements for IoT Platforms, defining a simple evaluation process strongly focused on vulnerability analysis to take into consideration the IoT ecosystem needs for optimized costs, timelines and resources. SESIP can be applied to individual components of IoT Platforms, composition between components, or directly to a full IoT Platform. RISC-V platforms are typical components of IoT Platforms for which security confidence demonstration is expected. Adoption of the industry-standard SESIP (https://globalplatform.org/sesip/) for compliance assessment to RISC-V Platform Security Model requirements produces those necessary evidences with reasonable and affordable efforts.
Speakers
EA

Eve Atallah

Security Evaluation Expert, NXP Semiconductors
I have a PhD in computer sciences and have been working in security evaluation laboratories before joining NXP Semiconductors where I am supporting the security certification of our IoT products and the development of adapted evaluation tools/methodologies, in particular SESIP. I... Read More →

Tuesday December 13, 2022 12:30pm - 12:50pm PST
Grand Ballroom 220 C
  Industry, Edge & IoT

12:30pm PST

StarFive's Efforts in Fuelling RISC-V Software Ecosystem - See Chin Liang, StarFive Technology
No ISA is useful without a software ecosystem. Building on top of StarFive VisionFive board success, StarFive Technology is working closely with RISC-V communities and partners to enrich the RISC-V software ecosystem further. 

From the architecture perspective, StarFive Technology is enabling SMP Linux on heterogeneous multicore which consists of core clusters that have slightly different RISC-V extensions. This includes the effort to ensure the standard Linux power management framework works seamlessly on the RISC-V platform. 

From the tools perspective, StarFive Technology is ensuring Yocto is easy to use and has better adoption through StarFive StarStudio, an eclipse-based IDE. To pair with the high-performance use cases, another tool-related effort includes enabling advanced features of Perf performance profiling tools to work on RISC-V platforms. 

In solution space, StarFive Technology is collaborating to push Debian RISC-V as part of a stable release, a critical milestone for the RISC-V distro. Last but not least, will provide a sneak peeks at StarFive's effort in enabling RISC-V's Chromium OS, the potential world's first RISC-V Chromebook.
Speakers
avatar for See Chin Liang

See Chin Liang

Director of Software Engineering, StarFive Technology
Leading StarFive Malaysia Design Center Software team, focusing on developing software solutions for the RISC-V ecosystem and CPU core, covering firmware, bootloader, Linux kernels, Yocto, distros such as Debian, tools solutions, and middleware. Previously, managed Embedded Software... Read More →

Tuesday December 13, 2022 12:30pm - 12:50pm PST
Hall 3
  Industry

12:30pm PST

Using RISC-V in Heterogeneous Solutions to Solve Compute Challenges Presented in the Automotive Industry - Naresh Gangadharan Menon, Imagination Technologies
The automotive industry is at an inflection point where major disruptions are happening. One of them is how the current compute architecture, where each function is attributed to an ECU, moves to a centralised architecture akin to a human brain. The central compute architecture uses data from different sensors around the vehicle, and AI inference to help take the right decisions. The requirements of these compute systems are expanding. The main ones being it should be able to work with any type and amount of data, be scalable in compute performance and should be efficient and simple to deploy. As the requirements for the system drive greater computation and efficiency, it is expected that the architecture becomes increasingly heterogenous which will require flexible programming models and software frameworks. This talk will give a good understanding where the automotive industry’s challenges in terms of compute are and how the next generation solutions will hinge on different forms of heterogeneous compute solutions.
Speakers
NG

Naresh Gangadharan Menon

Director of Product Management, CPU, Imagination Technologies
Naresh Menon is the Director of Product Management, CPU at Imagination. His role is to define the RISC-V CPU roadmap. He has over 16 years of previous experience with Arm building CPUs and working in its architecture group. Naresh is currently engaging with customers regarding Imagination’s... Read More →

RISC V Heterogeneous Compute in Automotive pdf
Tuesday December 13, 2022 12:30pm - 12:50pm PST
Grand Ballroom 220 B
  Industry, Automotive

12:30pm PST

OS-A SEE Explained - Aaron Durbin, Rivos Inc.
In this talk, the OS-A SEE specification will be explained in how it interacts with existing RISC-V specifications and other industry standards to target binary compatibility for rich Operating Systems. Further, the future use of the OS-A SEE specification will be described in how binary distributions can be created that are compatible across RISC-V systems. The talk will focus on the interfaces used by the Operating Systems to create that compatibility, including RISC-V system implementers' requirements.
Speakers
AD

Aaron Durbin

Principal Engineer, Rivos Inc.
Aaron Durbin is a principal engineer at Rivos Inc. He has more than 15 years of experience at Google productizing platforms in the embedded, client, and server space. In conducting that work, Aaron has worked closely with both hardware, software, and operators in designing computer... Read More →

2022 RISC V Summit OS A SEE Explained pdf
Tuesday December 13, 2022 12:30pm - 12:50pm PST
Grand Ballroom 220 A
  Technical, Software

12:50pm PST

Lunch Break
Endive and Radicchio, Radish, Mozzarella, Pumpkin Seeds, Apple Cider Vinaigrette (V/GF)
Roasted Chicken Thigh, Garlic Herb Gremolata, Caper Bechamel (GF)
Braised Beef Brisket, Port Wine Butter Sauce (GF)
Broiled Broccoli, Chili, Lemon (Vegan/GF/DF)
Smashed Potatoes, Chives (V/GF)
Fresh Fruit Tarts (Vegan)
Tuesday December 13, 2022 12:50pm - 2:15pm PST
Expo Hall - Hall 2
  Breaks + Event Experiences

1:00pm PST

Demo: RISC-V Cloud Lab - Ligang Zhang, Alibaba
This demo session introduces the RISC-V Cloud Lab. With RISC-V Cloud Lab, developers can access the RISC-V boards remotely, evaluate and benchmark RISC-V Core，develop and do demos easily on the boards.
Speakers
avatar for Ligang Zhang

Ligang Zhang

Staff Engineer, Alibaba
Ligang Zhang is a Technology Expert of the IoT R&D Department at Alibaba T-Head, his current job focuses on the Chip BSP verification and Embedded Operating System software verification and test automation framework of Embedded system product. He has constructed a RISC-V cloud lab... Read More →

Tuesday December 13, 2022 1:00pm - 1:10pm PST
Expo Hall - Hall 2 - Demo Theater
  Demo Theater

1:15pm PST

Demo: SmartNIC with OvS-DPDK on RISC-V - Kumar Sankaran, Ventana Micro Systems
This demo will show a SmartNIC application with RISC-V addressing the networking market segment. The demo will show a packet switching application between 2 VMs running on a host machine via the SmartNIC.
Speakers
avatar for Kumar Sankaran

Kumar Sankaran

VP SW and Solutions, Ventana
Kumar Sankaran heads the Software, Platform Engineering and Solutions Architecture functions for the Ventana high performance RISC-V based CPU solution designed for the Data Center, Edge, Networking, Storage, HPC and Mobile/IoT markets. He plays a key role within RISC-V International... Read More →

Tuesday December 13, 2022 1:15pm - 1:25pm PST
Expo Hall - Hall 2 - Demo Theater
  Demo Theater

1:30pm PST

Demo: RISC-V Models for Verification, Software Development and Architectural Exploration - Larry Lapides - Imperas Software Ltd.
Speakers
avatar for Larry Lapides

Larry Lapides

Vice President Sales, Imperas Software
Prior to joining Imperas, Larry ran sales at Averant and Calypto Design Systems. He was vice president of worldwide sales during the run-up to Verisity's IPO (the top performing IPO of 2001), and afterwards as Verisity solidified its position as the fifth largest EDA company. Before... Read More →

Imperas RISC V CPU models Summit 2022 pdf
Tuesday December 13, 2022 1:30pm - 1:40pm PST
Expo Hall - Hall 2 - Demo Theater
  Demo Theater

2:15pm PST

A Linux Distribution’s View on RISC-V - Heinrich Schuchardt, Canonical
Delivering a Linux distribution for an architecture in plain development is an exciting journey. The talk describes the challenges and opportunities seen while driving the RISC-V support in Ubuntu forward. We look at how Ubuntu delivers to the different market segments. A focus topic will be packages needed for high performance networking and storage.
Speakers
avatar for Heinrich Schuchardt

Heinrich Schuchardt

RISC-V lead engineer, Canonical
In Canonical's foundation team Heinrich Schuchardt is driving the RISC-V support in Ubuntu. As a long term contributor to open source software he is the maintainer of the UEFI implementation in the U-Boot firmware.

A Linux distribution’s view on RISC V pdf
Tuesday December 13, 2022 2:15pm - 2:35pm PST
Hall 3
  Industry, Building a Software Ecosystem

2:15pm PST

Is RISC-V HPC? RISC-V is HPC! - John Davis, Barcelona Supercomputing Center
Technology trends are mandating software/hardware co-design for HPC systems. An Open Standard Instruction Set Architecture (ISA) like RISC-V enables a powerful co-design paradigm. Presently, RISC-V lacks the maturity of other closed ISAs available on the market and many in the HPC community are unfamiliar with the details of RISC-V and/or incorrectly associate the ISA and development efforts as being limited to the embedded community. However, today, there is a focused and dedicated effort underway within the RISC-V community (well-funded companies, government support, and research) to bring RISC-V into the HPC space. As part of this presentation, we will update the larger community on our efforts (identify the HPC gaps, provide standardized ISA solutions and lead the effort to build up the ecosystem) as well as solicit feedback for prioritization of next steps. We will present the status of the current SW and HW RISC-V ecosystem with a focus on HPC. This is a call to action to address the gaps andprioritize efforts that target HPC with RISC-V hardware and the associated software stack.
Speakers
JD

John Davis

Director, Laboratory for Open Computer Architecture, Barcelona Supercomputing Center
John D. Davis is the Director of the Laboratory for Open Computer Architecture at Barcelona Supercomputing Center. He has published over 30-refereed conference and journal papers. He holds over 35 issued or pending patents in the USA and Europe. He has held several technical and executive... Read More →

RISC V IS HPC 20221213 pdf
Tuesday December 13, 2022 2:15pm - 2:35pm PST
Grand Ballroom 220 B
  Industry, High-Performance Computing & Data Centers

2:15pm PST

The Future of AI with RISC-V - Krste Asanovic, SiFive
This presentation, by the RISC-V founder, will highlight how RISC-V and vector compute are gaining momentum with AI and ML and computer vision and how it addresses challenges like managing power consumption, extra data movement, the need for multiple libraries, and issues with generational incompatibility. To solve these obstacles, many of the world’s largest data and device companies are turning to vector processing based on the RISC‑V Vector (RVV) 1.0 ISA. The presentation will include a walk on with a major US hyperscaler, to be named later, who will show how RISC-V is being integrated into datacenter applications and explain the reasons for their choice.
Speakers
avatar for Krste Asanovic

Krste Asanovic

Chair, RISC-V International
Krste Asanović is a Professor in the EECS Department at the University of California, Berkeley. He received a PhD in Computer Science from UC Berkeley in 1998 then joined the faculty at MIT, receiving tenure in 2005. He returned to join the faculty at Berkeley in 2007, where he co-founded... Read More →

Tuesday December 13, 2022 2:15pm - 2:35pm PST
Grand Ballroom 220 C
  Industry, High-Performance Computing & Data Centers

2:15pm PST

Progress in Porting Android onto RISC-V: Testing, Performance and Open Source - Mao Han, Alibaba
At the first quarter of this year, Alibaba T-Head reported supporting Android 12 on RISC-V based platform featuring multimedia, camera, Wi-Fi/Bluetooth and Neural Network. The upstream enablement of RISC-V has started within AOSP this September, Google approved and merged patches from us.

Since then most system features have been enabled on RISC-V architecture, and our main focus has been moved to the test suits, performance optimization and source code upstream inclusion. In this presentation, we will provide some insight into the progress of system validation through unit tests, CTS(Compatibility Test Suite) and VTS(Vendor Test Suite); the current status of performance analysis and the latest optimization updates. We will also present the community contribution to the Android on RISC-V support, and the status of upstream patch submission and inclusion.
Speakers
XM

Xiaohan Ma

Alibaba
avatar for Mao Han

Mao Han

Senior Engineer, Alibaba
Mao Han is working as a Senior Engineer in Alibaba T-Head, covering RISC-V support of Android system.He has many years of experience in Android, Linux, C library and profiling tools. Since 2020, he led a project to port RISC-V architecture onto Android system, and be the chair of... Read More →

Progress in Porting Android onto RISC V Maohan pdf
Tuesday December 13, 2022 2:15pm - 2:35pm PST
Grand Ballroom 220 A
  Technical

2:40pm PST

Empower Upstream ML Frameworks on RISC-V - Tiejun Chen, VMware
There is no doubt that RISC-V has great future, and has got noticed from IoT to Edge. Especially, we're seeing many efforts, like a variety of vector extension, happening towards the top edge computing workload - AI. However, on the one hand, these popular deep learning frameworks such as Tensorflow, Pytorch, etc, don't support RISC-V. Mostly users have to rewrite their own applications with new APIs releases by RISC-V vendors. On the other hand, in many cases customers need great ML performance with powerful HW accelerators like GPU, FPGA and so on, compared current RISC-V vector extension. Even, those RISC-V targets without vector extension or something similar, may worsen this problem because AI workloads cannot run on them at all! Here we'd like to review if-how we can enable those upstream ML frameworks on RISC-V targets seamlessly. With our solution, users can run their native AI application written with those upstream ML frameworks directly, but - 1. No code change; 2. Don't need to install ML frameworks on RISC-V essentially; 3. Enjoying AI accelerators - GPU, FPGA, whatever; 4. Accelerated by popular graph compliers. We'll show a demo to help understand the great value.
Speakers
avatar for Tiejun Chen

Tiejun Chen

Sr. Technical Lead, VMware
Tiejun Chen is Sr. technical leader from VMware OCTO, also strategic Representative of RISC-V International TSC 2023. He's been working on a lot of areas - cloud native, edge computing, ML/AI, RISC-V, WebAssembly, etc. He ever made many presentations at kubecon China 2021, Kube Edge... Read More →

Tuesday December 13, 2022 2:40pm - 3:00pm PST
Grand Ballroom 220 C
  Industry, Edge & IoT

2:40pm PST

Introducing the Highest Performance RISC-V Development Board: Next Generation SiFive HiFive - Sam Grove, SiFive & Nikhil Krishna Gopalakrishna, Intel
This talk will provide details about the next generation HiFive Development Board, which will be powered by the Intel and SiFive designed “Horse Creek” SoC. This is a much anticipated successor to the SiFive HiFive Unleashed and HiFIve Unmatched development boards, but with significantly higher performance and availability. This talk will provide details about the development board, including features, peripherals, and availability. This general purpose development board will be available to anyone in the RISC-V community to buy, use, and develop software for. This new product is currently expected to be the highest performance RISC-V silicon available for general purchase, and it is powered by a high-end multi-core SiFive Performance™ processor core and manufactured in the advanced Intel 4 process technology.
Speakers
avatar for Nikhil Krishna Gopalakrishna

Nikhil Krishna Gopalakrishna

Principal Engineer, Intel
Principal Engineer at Intel and architect for Intel's first RISCV silicon - Horse Creek. Industry experience of 20 years across different countries. 15+ years of experience on ARM based SOCs for automotive market. Been with Intel for the past 6 years with roles spanning across, design... Read More →
avatar for Sam Grove

Sam Grove

Director Product Management - Software, SiFive
Samuel (Sam) Grove is the Director of Product Management for software at SiFive. He has more than15 years of experience in designing embedded software, operating systems, and community-driven open- source software development. Prior to joining SiFive, he worked at Arm in various roles... Read More →

RISC V Summit 2022 Introducing the Highest Performance RISC V Development Board pdf
Tuesday December 13, 2022 2:40pm - 3:00pm PST
Hall 3
  Industry, Building a Software Ecosystem

2:40pm PST

RISC-V Powered SoM Based Products and HPC Native Development - Yuning Liang, Xcalibyte
We will announce：  
The world first 12nm RISC-V SoC powered SoM based Laptop ROMA with 3D AR Glasses, and its sibling product.  
28nm RISC-V SoC powered SoM based AI Robot. 
And last but not least, ROMA’s Core RISC-V SoC powered SoM module and its base development board. 

The presentation will also give analysis of the importance of native software development approach, as well as announcement of Xcalibyte HPC native compiler running on laptop ROMA and demo the development of SeL4 application on SoM based development board or product.
Speakers
avatar for Yuning Liang

Yuning Liang

Founder & CEO, Xcalibyte
Yuning is the founder and CEO of Xcalibyte and Advisor of Deepcomputing which makes RISC-V powered SoM based electronic products, from first RISC-V laptop ROMA, to AR glasses, AI Robot and AV cars.. Xcalibyte specialised in：  Original MIPS/SGI Open64 based HPC compiler, now made... Read More →

Tuesday December 13, 2022 2:40pm - 3:00pm PST
Grand Ballroom 220 B
  Industry

2:40pm PST

The RISC-V Vector Cryptography Extensions - G. Richard Newell, Microchip Technology Inc. & Ken Dockser, Rivos Inc.
In 2021 the lightweight Scalar Cryptography and Entropy Source extensions were ratified, aimed at RV32 and RV64 CPUs. This year the Vector Cryptography Extensions will be finished. These include Vector ISA extensions for efficiently performing AES, GHASH, SHA2, SM3, and SM4 cryptographic calculations using the large registers made available by the Vector Extension, mainly targeting higher-end systems like personal computers and servers, though they will also run efficiently on smaller vector machines with 128-bit or longer vector registers. These extensions include some vector bit-manipulation instructions that help optimize kernels based on the cryptographic instructions as well as supporting other algorithms such as prime- and binary-field ECC and SHA3, which is important for post-quantum cryptography. This talk reviews the Vector Cryptographic Extensions, the rationale behind them, and how they are used to efficiently implement cryptographic kernels.
Speakers
RN

Richard Newell

Associate Technical Fellow, Microchip Technology Inc
Richard Newell is responsible for architecting the security features for Microchip's current and future generations of FPGAs and SoC FPGAs. Richard has an electrical engineering background with over 45 years of experience in analog and digital signal processing, cryptography, control... Read More →
avatar for Ken Dockser

Ken Dockser

CPU Architect, Rivos Inc.
Ken Dockser is a CPU architect at Rivos Inc, where he defines the macro-architecture for high-performance RISC-V CPUs. Ken's previous position was at Qualcomm where he headed up Processor Research (concentrating on RISC-V) as a Senior Director. Before that he was a CPU architect for... Read More →

Vector Crypto 2022 Summit pdf
Tuesday December 13, 2022 2:40pm - 3:00pm PST
Grand Ballroom 220 A
  Technical, ISA

3:05pm PST

Democratizing Innovation in Automotive with RISC-V and Open Source - Gordan Markuš, Canonical Ltd.
Over the past years, the mobility industry has been facing rapid disruption. The growing need for efficient, performant, secure, and safe solutions increases the complexity of in-vehicle hardware and software. These trends impact the hardware and software requirements, and the vehicle architecture as a whole. In response, the car manufacturers seek to evolve their supply chain and software strategy to enable the creation of reliable and reusable platforms. Open hardware standards complemented with industry standards and open source software is a winning combination for creating a vibrant ecosystem primed for innovation. This presentation aims to give an introduction to automotive concepts, E/E (electrical/electronic) vehicle architectures, the trends and challenges the industry is currently facing. The speaker will highlight why RISC-V is a perfect solution to a number of those challenges.
Speakers
avatar for Gordan Markus

Gordan Markus

Silicon Alliances Partner Manager, Canonical Ltd.
With more than a decade in engineering, business development, and leadership roles working with open source software, Gordan is a leader in Canonical's Silicon Alliances organization, developing strategic relationships with the RISC-V ecosystem and various other semiconductor companies... Read More →

RISC V Summit North America 2022 Gordan Markus Democratizing Innovation in Automotive with RISC V and Open Source pdf
Tuesday December 13, 2022 3:05pm - 3:25pm PST
Grand Ballroom 220 B
  Industry, Automotive

3:05pm PST

Panel: It Takes a Village… to Build an Ecosystem - Amber Huffman, Google; Dan Mender, Green Hills Software; Peter Lewin, Imagination Technologies; Rob Aitken, Synopsys; Phil Dworsky, SiFive
RISC-V is taking off as one of the three primary processor architectures, being used by top semiconductor companies in products targeting numerous markets. Organizations are seeing not only the technical benefits, but also the potential for the ecosystem to grow significantly over the next few years based on the open architecture and broad support. This panel will explore where we are today in developing that RISC-V ecosystem, and where we need to continue to invest to fill it out, including for markets like Automotive.
Speakers
BB

Bob Brennan

VP&GM Customer Solutions Engineering, Intel Foundry Services, Intel
Bob Brennan is Vice President of Customer Solutions Engineering for Intel Foundry Services at Intel Corporation. He is responsible for leading the delivery of end-to-end design solutions to help IFS customers use Intel’s portfolio of unique IPs and design technology in their product... Read More →
AH

Amber Huffman

Principal Engineer, Google
Amber Huffman is a Principal Engineer in Google Cloud responsible for leading industry engagement efforts in the data center ecosystem across servers, storage, networking, accelerators, power, cooling, and security. Prior to joining Google, she spent 25 years at Intel serving as an... Read More →
avatar for Peter Lewin

Peter Lewin

Director of CPU Ecosystems, Imagination Technologies
Pete looks after the RISC-V CPU ecosystem at Imagination technologies, and is chair of the RISC-V Automotive Special Interest Group. Prior to this he worked for over 20 years in the CPU IP business in various technical, marketing and business roles supporting complex ecosystems encompassing... Read More →
avatar for Phil Dworsky

Phil Dworsky

Head of Strategic Alliances, SiFive
Phil Dworsky, a veteran of more than 35 years in EDA and IP, heads SiFive’s worldwide strategic alliances. Prior to SiFive, Phil led Synopsys’ strategic alliances and was publisher of Synopsys Press, an imprint of Synopsys that he founded to create and deliver technical and business... Read More →
DM

Dan Mender

VP Business Development, Green Hills Software
As vice president of business development, Dan Mender is responsible for developing, implementing and maintaining the company's global direction, product roadmap, partnerships, alliances and thought leadership across a number of vertical industries that include automotive, industrial... Read More →
RA

Rob Aitken

Distinguished Architect, Synopsys
Rob Aitken is a Distinguished Architect at Synopsys. Prior to Synopsys, he was an Arm Fellow responsible for technology direction at Arm Research. He works on hardware security issues, low power design, and emerging technologies. He has worked on 15+ Moore’s law nodes and has published... Read More →

Tuesday December 13, 2022 3:05pm - 3:25pm PST
Hall 3
  Industry, Corporate and Market Development (including investing)

3:05pm PST

Redefining the Embedded Development Landscape with Software-defined SoCs - Mark Lippett, XMOS
In this session, we explore the way in which software-defined SoCs are redefining the embedded development landscape by using RISC-V programmable threads.
Speakers
avatar for Mark Lippett

Mark Lippett

XMOS, CEO
Mark started with XMOS in 2008 in the role of VP Engineering, before being appointed as COO and taking the helm as CEO in 2016. Mark has extensive experience across the electronics industry, with involvement in both blue-chip and start-up companies.Prior to XMOS Mark was founder and... Read More →

XMOS Industry Session RISC V Summit 2022 pdf
Tuesday December 13, 2022 3:05pm - 3:25pm PST
Grand Ballroom 220 C
  Industry, Edge & IoT

3:05pm PST

I/O Virtualization Use Cases and the RISC-V IOMMU Overview - Ved Shanbhogue, Rivos Inc.
The RISC-V IOMMU technology unlocks a slew of new and exciting capabilities such as device passthrough, shared virtual memory, interrupt redirection, etc. and is a critical component to address functional, security, and safety requirements of SoC targeting a wide array of usages across enterprise, cloud, HPC, industrial, telecom, automotive, etc. In the talk will focus on following topics: - Motivations and use cases - IOMMU Integrating models - Software frameworks - and IOMMU role in Confidential computing Finally, we will provide a brief overview of the RISC-V IOMMU technology under development. This talk does not assume prior knowledge about IO and IO virtualization technologies and will mostly cover the underlying concepts to help the audience familiarize with the IOMMU technology and its usages.
Speakers
avatar for Ved Shanbhogue

Ved Shanbhogue

Member of Technical Staff, Rivos Inc.
Ved Shanbhogue is with Rivos Inc. and a key contributor to RISC-V. He has contributed to development of various ratified and in-progress RISC-V ISA (Zawrs, Zacas, Zicfiss, Zicfilp) and non-ISA extensions (IOMMU, CBQRI, Server SoC HW spec., RAS ERI). He chairs the SoC infrastructure... Read More →

RISC V summit 2022 IOMMU pdf
Tuesday December 13, 2022 3:05pm - 3:25pm PST
Grand Ballroom 220 A
  Technical, System-on-a-Chip

3:25pm PST

Afternoon Break
Movie Night (V)
Cheddar Cheese Popcorn, Soft Pretzels with Grain Mustard, 100 Grand Bars, Oreo Dusted Churro

Crudité of Seasonal Vegetables, Holland Red Gouda, Fruit Chutneys, Crackers, Roasted Garlic Hummus
Tuesday December 13, 2022 3:25pm - 3:55pm PST
Expo Hall - Hall 2
  Breaks + Event Experiences

3:30pm PST

Demo: RISC-V Dual Lock-step Implementation for Safety and Security Applications - Paul Elliott, Codasip
In this session, we demonstrate how a secure dual-core lockstep processor can be used to detect and trap faults injected at the hardware level, no matter if that fault was caused by a system malfunction or a deliberate attack. To enable fault testing the design is annotated with smart fault injectors, a functionality that Codasip intends to provide to automate and aid the design of resilient compute systems. The smart fault injectors can be adapted to different fault models addressing the automotive functional safety ISO 26262:2018 as well as the automotive cybersecurity standard ISO/SAE 21434:2021. A proven method in other architectures, dual lockstep enables fault detection no matter what caused the fault.
Speakers
avatar for Paul Elliott

Paul Elliott

Security and Safety Architect, Codasip
Paul Elliott is a senior Security and Safety architect at Codasip Labs who has spent his career working in the semiconductor industry. He is a specialist in IoT hardware security, who helped build and went on to lead a new security architecture team at STMicroelectronics. Following... Read More →

Tuesday December 13, 2022 3:30pm - 3:40pm PST
Expo Hall - Hall 2 - Demo Theater
  Demo Theater

3:45pm PST

Demo: Smart Embedded Vision with PolarFire® SoC FPGA - Krishnakumar (KK), Microchip
License plate detection using PolarFire® SoC Video Kit. 
Speakers
avatar for Krishnakumar (KK)

Krishnakumar (KK)

Microchip
Krishnakumar R (KK) is a senior marketing manager for Microchip’s FieldProgrammable Gate Array (FPGA) business unit. He as over 20 years of industryexperience. His role spreads across product marketing, ecosystem development andbusiness development for various FPGA product families... Read More →

Smart Embedded Vision with PolarFire SoC FPGA Demo Theater pdf
Tuesday December 13, 2022 3:45pm - 3:55pm PST
Expo Hall - Hall 2 - Demo Theater
  Demo Theater

3:55pm PST

IoT True Wireless Stereo Applications Shine with RISC-V and HiFi DSP - Casey Ng, Cadence
The RISC-V CPU and HiFi core combine to make an optimal solution. The RISC-V architecture runs the Bluetooth stack and other operating software, while the HiFi runs the audio related software. With its ability to modularize and customize for only the supported instructions, the RISC-V CPU helps optimize the cost, while the HiFi core provides the essential audio processing such as the LC3 codec and advanced features like Always On Keyword Spotting. Such flexibility offer IoT and Bluetooth applications power and cost-optimized designs. In addition, the RISC-V PMP (physical memory protection) and support for machine/supervisor/user mode makes the processor resilient to support supply chain security and protect the software IPs. Several architecture examples will be provided and discussions on their features, use cases and the design resources to bring products to the market.
Speakers
avatar for Casey Ng

Casey Ng

Audio Product Marketing Director, Cadence
Casey co-founded Nuforce, a high-performance audio brand that re-invented Class-D amplifiers with pure-analog modulation technique, which it had won Best product awards worldwide, as the VP of Engineering in Nuforce, he designed and brought to market over 50 high-performance home... Read More →

TWS Application RISC V and HiFi PC CASEYNG pdf
Tuesday December 13, 2022 3:55pm - 4:15pm PST
Grand Ballroom 220 C
  Industry, Edge & IoT

3:55pm PST

Ocelot: Open Source Vector Unit - Srikanth Arekapudi & Dongjie Xie, Tenstorrent
Ocelot is a RISCV based Vector design implemented by Tenstorrent that was open sourced to help advance the adoption of RISCV ISA. We believe Vector operations have significant use-cases, from HPC to ML, and the availability of a parameterized vector design that supports VLEN up to 512 provides a fast adoption path for users, whether in academia or industry. Ocelot Vector design is integrated with the BOOM core in the Chipyard environment. It can also be used with any other RISCV based design. It has been functionally verified with 1000s of arch and uArch tests as well as synthesized under an advanced tech node. We also generated performance data by running Vector sensitive workloads and identified glass jaws that are a result of certain architecture decisions. In this presentation we would go over key data generated with Ocelot as well as our vision for future work on V-extensions, with an emphasis on how these would provide a key advantage over similar implementations on x86 and ARM ISAs. Finally, we would like to highlight some areas for aggressive compiler optimizations that would increase the performance of the Vector unit. https://github.com/tenstorrent/riscv-ocelot
Speakers
SA

Srikanth Arekapudi

Fellow, Tenstorrent
Srikanth Arekapudi is currently a Fellow at Tenstorrent, where he leads the high performance RISCV CPU design team. He was one of the early employees at Cerebras systems and involved in the design of several aspects of Wafer Scale Engine for machine learning. Prior to that he was... Read More →
DX

Dongjie Xie

Staff Engineer, Tenstorrent
Dongjie is currently working at Tenstorrent and is involved in design of high performance vector unit. Prior to Tenstorrent, Dongjie worked at Apple and has made significant contributions to several aspects of GPU designs. He holds BS and MS degrees from University of Illinois Urbana... Read More →

Tenstorrent Ocelot RiscV Summit 2022 pdf
Tuesday December 13, 2022 3:55pm - 4:15pm PST
Grand Ballroom 220 A
  Industry, High-Performance Computing & Data Centers

3:55pm PST

Panel: Building a Scalable RISC-V Software Ecosystem - John Hengeveld, Intel; Kumar Sankaran, Ventana; Leendert Van Doorn, Qualcomm; Steve Wanless, Red Hat; Olivier Bernard, AWS; Makeljana Shkuti, VRULL
Panelists would be industry partners from across the stack – HW, FW, OS, Tools, etc. We would focus the session on gaps, opportunities, and things that we can do together that cross boundaries.
Speakers
avatar for Makeljana Shkuti
avatar for Leendert van Doorn

Leendert van Doorn

SVP Engineering, Qualcomm
Leendert van Doorn is a Senior Vice President at Qualcomm which he recently (June 2022)joined to help with Qualcomm's datacenter, software strategy and AI Software efforts. Beforethat, he was a Distinguished Engineer/VP in Microsoft's Azure Core team where he is bestknown for his... Read More →
SW

Steve Wanless

Business Strategist Linux, Red Hat
OB

Olivier Bernard

IOT and Robotics Services, AWS
JH

John Hengeveld

SW Product Management Director, Intel
30 year veteran of the semiconductor industry. John is Director of SW Product Management at Intel working with Intel Foundry Servies team to enable non x86 architectures for success in emerging applications. Most recently John spent 8 years as Strategy Director for Arm’s Intellectual... Read More →
avatar for Kumar Sankaran

Kumar Sankaran

VP SW and Solutions, Ventana
Kumar Sankaran heads the Software, Platform Engineering and Solutions Architecture functions for the Ventana high performance RISC-V based CPU solution designed for the Data Center, Edge, Networking, Storage, HPC and Mobile/IoT markets. He plays a key role within RISC-V International... Read More →

Tuesday December 13, 2022 3:55pm - 5:05pm PST
Grand Ballroom 220 B
  Industry, Building a Software Ecosystem

4:20pm PST

RISC-V for Aerospace and Defense Applications - Tom Leahy, SiFive
With recent announcements from NASA and others who are embracing the benefits of RISC-V this talk will explore the benefits that are attracting so much attention. With examples from existing users such as NASA, DARPA, the DOD and DOE, we'll look at how the broad and growing RISC-V ecosystem and how its expected long life, open- standards, flexibility and power advantages and other features are creating huge opportunities for RISC-V suppliers. We'll also touch upon the Chips act and what that means to suppliers and customers.
Speakers
TL

Tom Leahy

Head of Aerospace and Defense Business Development, SiFive
Tom is a new member of SiFive as the Head of Aerospace and Defense Business Development with responsibilities of driving DoD, DIB and ecosystem developments and creating technology partnerships to advance the capabilities of the warfighter. Prior to SiFive, he held strategic senior... Read More →

Tuesday December 13, 2022 4:20pm - 4:40pm PST
Grand Ballroom 220 A
  Industry, High-Performance Computing & Data Centers

4:20pm PST

The New Verification Ecosystem that Supports RISC-V Verification for all Adopters - Lee Moore, Imperas Software & John Sotiropoulos, Breker Verification Systems
The RISC-V design freedoms have enabled implementers to innovate new and creative solutions. As a design progresses from concept to completion, the flexibility of RISC-V has implications for the hardware functional verification teams. This talk covers the latest developments in the RISC-V verification ecosystem to address new approaches for processor verification. These include: open standards to support universal testbenches and VIP (Verification IP) reuse, coverage libraries and quantitative measures for test infrastructure quality, and novel techniques to verify cache coherency and SoC integration. Based on examples from several popular open-source cores this talk will provide guidelines that can help both open-source and commercial projects address the RISC-V functional verification challenge.
Speakers
avatar for John Sotiropoulos

John Sotiropoulos

Principal Applications Engineer, Breker Verification Systems
John is a Principal Applications Engineer with Breker Verification Systems, working on Test Suite Synthesis and Portable Stimulus solutions. John has extensive verification experience in senior engineering roles at companies such as Intel, Facebook and Draper Labs. He also worked... Read More →
avatar for Lee Moore

Lee Moore

Lead Applications Engineer, Imperas Software
Lee Moore is the lead engineer at Imperas for RISC-V processor models and simulation tools. Prior to Imperas, Lee worked as a senior consulting engineer for EDA vendors such as Co-Design Automation and Ambit, and for ASIC vendor NEC Electronics. Lee is also a private pilot, and recently... Read More →

Tuesday December 13, 2022 4:20pm - 4:40pm PST
Grand Ballroom 220 C
  Industry, Building a Software Ecosystem

4:45pm PST

Future is Sideways - Not Only Up and Right - John Min, Andes Technology USA
Andes is always working on delivering the right solutions for customers. That does not necessarily mean Up and Right. Going sideways can yield best CPUs for embedded applications. Andes is introducing multiple new processors optimized for IoT and Automotive markets. We will discuss the new processors and new application areas – new frontiers for RISC-V.
Speakers
avatar for John Min

John Min

Director of Solution Engineering, Andes Technology USA
John Min is Director of Solution Engineering at Andes USA. He has extensive background in Processing – CPU, DSP and ASIC.Prior to Andes, John spent last 30 years in Processor companies like SiFive, MIPS and ARC in various technical roles.He has also worked in consumer electronics... Read More →

Tuesday December 13, 2022 4:45pm - 5:05pm PST
Grand Ballroom 220 C
  Industry, Edge & IoT

4:45pm PST

Real World Results using Thousands of RISC-V Cores for AI and Beyond - Dave Ditzel, Esperanto Technologies, Inc
Esperanto’s ET-SoC-1 features over a thousand 64-bit RISC-V vector/tensor cores on a single 7nm chip. This product started shipping to customers in 2022. This presentation will discuss the architecture of the ET-SoC-1 and how it is incorporated into systems appropriate for data centers. This presentation will present real world results in both performance and performance per watt. We will show a system example where a single rack could hold over 300,000 RISC-V processors. The results demonstrate that one can achieve excellent results for accelerating machine learning and other applications by building on top of the general-purpose RISC-V instruction set. One does not have to resort to GPUs to get good performance per watt, RISC-V is a better alternative. This talk will also discuss Esperanto’s roadmap, which will incorporate chiplet inter-operability and much higher performance, improved performance per watt, and larger number of cores per package.
Speakers
avatar for Dave Ditzel

Dave Ditzel

CTO, Esperanto Technologies

Esperanto Ditzel Thousands of RISC V Cores for AI and Beyond for RISC V Summit2022 pdf
Tuesday December 13, 2022 4:45pm - 5:05pm PST
Grand Ballroom 220 A
  Industry, High-Performance Computing & Data Centers

5:10pm PST

Onsite Attendee Reception - Sponsored by Andes Technology
Everyone is invited to join their fellow attendees for drinks, appetizers, and networking after sessions.

Cinnamon & Sugar Dusted Churros with Caramel and Chocolate Sauce
Watermelon and pineapple w/ Tajin skewers
Watermelon and pineapple w/ NO Tajin skewers

Street Tacos (GF)
Includes: Soft Corn Tortillas, Cilantro, Onion, Cabbage, Jalapeno, Queso, Lime, Tajin, Guajillo Salsa
- Pulled Beef Brisket
- Mole Spiced Chayote, Peppers and Onions

Chips and Dip (V/GF)
Kettle Chips, Tortilla Chips, House Made Guajillo Salsa, Toasted Onion Dip, Guacamole

Elote (V/GF)
1/2 Cobb Each
- Mole, Cotija, Tajin, Cilantro, Lime
- Tahini, Sumac, Mint, Feta Cheese, Red Onion
Tuesday December 13, 2022 5:10pm - 7:00pm PST
Expo Hall - Hall 2
  Breaks + Event Experiences
 
Wednesday, December 14
 

8:30am PST

Registration
Wednesday December 14, 2022 8:30am - 4:00pm PST
Hall 2 Foyer
  Registration

9:00am PST

Keynote: State of the Union - Krste Asanović, Professor, UC Berkeley & Chair of RISC-V International
Speakers
avatar for Krste Asanovic

Krste Asanovic

Chair, RISC-V International
Krste Asanović is a Professor in the EECS Department at the University of California, Berkeley. He received a PhD in Computer Science from UC Berkeley in 1998 then joined the faculty at MIT, receiving tenure in 2005. He returned to join the faculty at Berkeley in 2007, where he co-founded... Read More →

RISCV 20221214 StateOfUnion pdf
Wednesday December 14, 2022 9:00am - 9:20am PST
Hall 3
  Keynote Sessions
  • Slides Attached Yes

9:20am PST

Keynote: The Android Open Source Project and RISC-V - Lars Bergstrom, Google Director of Engineering, Android Platform Programming Languages
The Android Open Source Project (AOSP) allows everyone to create a full, production-quality operating system for products and can be ported to nearly any device. In this talk, I will discuss the status of RISC-V support in AOSP as well as how you can build, test, and contribute back to it.
Speakers
avatar for Lars Bergstrom

Lars Bergstrom

Google Director of Engineering, Android Platform Programming Languages
Lars Bergstrom is a Director of Engineering at Google on the Android team, working on their platform programming languages, including Java, C/C++, and Rust and the supporting tools and libraries. He also serves as Google’s Corporate Director to the Rust Foundation. Before Google... Read More →

Wednesday December 14, 2022 9:20am - 9:40am PST
Hall 3
  Keynote Sessions

9:45am PST

Keynote: HPSC – Radically Advancing the Capabilities of Space-based Computing - Pete Fiacco, Member HPSC Leadership Team, JPL Consultant, Managing Partner, Executive Technology Consulting
Speakers
avatar for Pete Fiacco

Pete Fiacco

Member HPSC Leadership Team, JPL Consultant, Managing Partner, Executive Technology Consulting
Pete Fiacco is an award-winning CTO, Founder and technology leader. A recognized semiconductor industry expert on SOCs (System-on-Chip) that focus on Storage, CPU, GPU, FPGA and networking technologies. Pete built and led teams that have delivered thousands of key industry innovations... Read More →

Wednesday December 14, 2022 9:45am - 10:00am PST
Hall 3
  Keynote Sessions

10:00am PST

RISC-V Spotlight: Expanding the RISC-V Horizon and Beyond - Charlie Su, President and CTO, Andes Technology
 RISC-V ecosystem is growing in an unprecedented speed and Andes is a key driving force by offering rich processor IP solutions. In this talk, we will show a wide range of applications which have adopted RISC-V solutions and we will introduce new product lines to further expand the RISC-V horizon.
Speakers
avatar for Charlie Su

Charlie Su

President and CTO, Andes Technology
Dr. Charlie Su, Co-founder, President and CTO of Andes Technology, has overseen engineering and marketing since the company started in 2005. Under his leadership, Andes developed processor IP solutions based on its own ISA before joining the RISC-V Foundation as a founding member... Read More →

4. Charlie Su FINAL pdf
Wednesday December 14, 2022 10:00am - 10:15am PST
Hall 3
  Keynote Sessions
  • Slides Attached Yes

10:20am PST

RISC-V Spotlight: Scrum for Success - Shreyas Derashri, VP of Compute, Imagination Technologies
Innovation is happening across the RISC-V community, but can we work together to move RISC-V forward to meet diverse needs? Every market area and use case has different requirements and one size will not fit all.

To meet the needs of a wide range of use cases, our approach is to bring together different processor offerings to create innovative heterogeneous compute solutions.

In this talk, Imagination, an IP leader for over 20 years offering world-class GPU, CPU and AI IP, will share what it has learnt about the future of heterogeneous compute and how the RISC-V community can scrum together to continue the evolution of the semiconductor market.
Speakers
avatar for Shreyas Derashri

Shreyas Derashri

VP of Compute, Imagination Technologies
Shreyas is currently Vice President of Compute at Imagination, responsible for Imagination’s CPU, AI and Heterogeneous compute products and solutions. He has spent 20 years in the technology industry both in start-ups and in large corporations in various roles. He started his journey... Read More →

Wednesday December 14, 2022 10:20am - 10:30am PST
Hall 3
  Keynote Sessions

10:30am PST

Keynote: Awards Presentation


Wednesday December 14, 2022 10:30am - 10:40am PST
Hall 3
  Keynote Sessions

10:45am PST

Morning Break
Freshly Baked Danishes - Berry, Apple, Cheese
Yogurt & Granola
- Sweet Sesame Tahini, Raisins, Sesame Seeds V
- Chocolate Chip, Blueberry, Honey V
Wednesday December 14, 2022 10:45am - 11:15am PST
Expo Hall - Hall 2
  Breaks + Event Experiences

10:45am PST

Expo Hall
Wednesday December 14, 2022 10:45am - 4:00pm PST
Expo Hall - Hall 2
  Breaks + Event Experiences

10:50am PST

Demo: CORE-V MCU with CV32E40P Processor Core - Dan Gross, AWS
OpenHW Group's CORE-V MCU, taping out in GF22 fdx, features the fully verified open-source CV32E40P processor. With full ecosystem support - Dev-Kit, FPGA implementation, SDK, tool chains, FreeRTOS, and debugger support - CORE-V MCU is an ideal platform for embedded system designs.
Speakers
avatar for Dan Gross

Dan Gross

Sr. Developer Advocate, AWS

Wednesday December 14, 2022 10:50am - 11:00am PST
Expo Hall - Hall 2 - Demo Theater
  Demo Theater

11:05am PST

Demo: Storage Acceleration with SPDK on RISC-V - Kumar Sankaran, Ventana Micro Systems
This demo will show the benefits of using SPDK in a storage application on a RISC-V platform addressing the storage market segment. The demo will show performance benefits of using SPDK and also an NVMe-oTCP application where a remote device on an SPDK enabled RISC-V target server is accessed from a client host system.
Speakers
avatar for Kumar Sankaran

Kumar Sankaran

VP SW and Solutions, Ventana
Kumar Sankaran heads the Software, Platform Engineering and Solutions Architecture functions for the Ventana high performance RISC-V based CPU solution designed for the Data Center, Edge, Networking, Storage, HPC and Mobile/IoT markets. He plays a key role within RISC-V International... Read More →

Wednesday December 14, 2022 11:05am - 11:15am PST
Expo Hall - Hall 2 - Demo Theater
  Demo Theater

11:15am PST

KUtrace For RISC-V - Richard Sites
KUtrace is a low-overhead (less than 1%) Linux software tool to identify where all the execution and waiting time goes in a running system. Using a small number of kernel patches, it traces every transition between kernel- and user-mode execution using tiny four-byte entries per event, recorded into a kernel trace buffer. Postprocessing turns these into dynamic HTML pictures of what every CPU core is doing every nanosecond, complete with all the wakeup interactions between threads, and with instruction per cycle (IPC) values for every microsecond-scale timespan showing hardware interference between programs and between the operating system and user code. An early version of this has been in use at Google for over ten years, revealing the root causes of unusual transaction latency. KUtrace works for any executables written in any language, completely unmodified. The port to the RISC-V Unmatched board revealed several implementation drawbacks that we will briefly discuss.
Speakers
avatar for Richard Sites

Richard Sites

retired, retired
Dr. Richard L. Sites wrote his first computer program in 1959 and has spent most of his career at the boundary between hardware and software, with a particular interest in CPU/ software performance. He past work includes VAX microcode, DEC Alpha co-architect, and inventing the performance... Read More →

sites KUtrace for RISC V pdf
Wednesday December 14, 2022 11:15am - 11:35am PST
Grand Ballroom 220 A
  Technical, Software

11:15am PST

New DSP Extensions to the Embench Benchmark Suite - Ray Simar, Rice University
The ability to extend and optimize the RISC-V ISA for a number of new developing embedded applications has highlighted the need for a suite of benchmarks targeted at the embedded microprocessor space. This is the goal of the Embench effort, chaired by Dave Patterson and Jeremy Bennett. As part of this effort, the development of a new set of DSP benchmarks for the embedded space is under way. The use of DSP algorithms is critical to many applications areas. At Rice University, with support of the Embench team, we have been developing an initial benchmark suite focused on three key DSP benchmarks that will be familiar to many: FIR (Finite Impulse Response filter), IIR (Infinite Impulse Response filter), and FFT (Fast discrete Fourier Transform). All of the benchmarks are written in C and can be easily ported to different platforms. We avoid creating special case versions of the benchmarks that might offer particular advantages to some microprocessors. Nonetheless, the benchmarks are written so that they should be suitable for illustrating the performance of the new generation of vector microprocessors.
Speakers
avatar for Ray Simar

Ray Simar

Professor in the Practice, Rice University
Ray is a Professor in the Practice in Electrical and Computer Engineering at Rice University. He is a cofounder of the new RVR (RISC-V at Rice) Lab. The RVR Lab is a new experiential computer engineering research and teaching lab placing both undergraduate and graduate students at... Read More →

Embench DSP benchmarks RISC V Summit Dec 2022 Ray Simar V5 pdf
Wednesday December 14, 2022 11:15am - 11:35am PST
Grand Ballroom 220 C
  Technical, ISA

11:15am PST

SCAIE-V: A Scalable Open-source Interface for Flexible and Portable ISA Extensions - Andreas Koch, TU Darmstadt
Custom instructions or ISA Extensions (here abbreviated as ISAX) are a key means to improve the performance or efficiency of a processor core. The open RISC-V ISA has been designed right from the start to allow such extensions, with the wide spectrum of available open-source processor cores enabling the practical implementation of cores realizing the ISAX. However, not all cores provide extension interfaces, and those that do often have interfaces that are limited in ISAX functionality, or aimed at specific accelerator attachments. SCAIE-V aims to address these issues. It is a flexible interface, allowing the realization of ISAX ranging from simple combinational, to multi-cycle, to memory and control flow custom instructions, as well as advanced features such as decoupled execution. The interface is scalable, in that the area overhead for the more advanced features is only paid if instructions requiring those features are actually used. SCAIE-V is applicable to a wide spectrum of core microarchitectures, and thus enables the portability of ISAX even between very different cores. It also makes a suitable target for the high-level synthesis of ISAX from abstract descriptions.
Speakers
avatar for Andreas Koch

Andreas Koch

Professor, TU Darmstadt
Andreas Koch is a professor at Technical University Darmstadt Germany, where he leads the Embedded Systems & Applications Group since 2005. His main research focus are domain-specific computing architectures, accelerators, and the associated programming tools. He has contributed to... Read More →

RV Summit2022 SCAIE V AKoch TUDarmstadt pdf
Wednesday December 14, 2022 11:15am - 11:35am PST
Grand Ballroom 220 B
  Technical, ISA

11:40am PST

Automatic Test Generation and Verification for RISC-V Vector Extension - Shenwei Hu & Xi Wang, RIOS Lab, Tsinghua University
RISC-V Vector (RVV) extension has been proposed to achieve high-performance executions of vectorization computing. However, RVV introduces 217 new instructions, 7 new CSRs and diverse configuration parameters. Such complexity makes it difficult to produce a golden test suite for developers, especially due to the combinations of distinct RVV parameter configurations like vlen, vsew, vmul, etc. In order to address such issue, RIOS Lab cooperate with the RISC-V foundation and design a configurable RVV test generator for the RISC-V community. We first designed and implemented the RVV Sail Model as the golden model to execute the RVV instructions. With the Sail model support, we further developed a configurable test generator with quantifiable coverage for RISC-V Vector Extension. Users are able to select instructions to be tested and set configuration parameters combination, then the associative tests are automatically generated. The entire flow is compatible with the latest RISCOF infrastructures which are massively utilized by RISC-V tests. We will also demonstrate our RVV support for RISCV-ISAC and RISCOF to obtain a quantitative coverage report.
Speakers
avatar for Shenwei Hu

Shenwei Hu

Master Student, RIOS Lab, Tsinghua University
Mr. Shenwei Hu is a Master student at the RISC-V International Open Source Laboratory (RIOS Lab), Tsinghua University. His advisor is Dr. Zhangxi Tan and his research interests include computer architecture, RISC-V software infrastructures and toolchains. Email: shenwei.h@rioslab.org... Read More →
XW

Xi Wang

Postdoctoral Researcher, RIOS Lab, Tsinghua University
Dr. Xi Wang is a Postdoctoral Researcher at the RISC-V International Open Source Laboratory (RIOS Lab), Tsinghua University. Dr. Wang has over 7-year experiences in RISC-V computer architecture design. His research interests include computer architecture, RISC-V processor design... Read More →

RVV ATG+Pre pdf
Wednesday December 14, 2022 11:40am - 12:00pm PST
Grand Ballroom 220 B
  Technical, Software

11:40am PST

HW-SW Co-development for RISC-V Based Secure ML Systems with the Sparrow Project and Renode - Michael Gielda, Antmicro & Kai Yick, Google
Sparrow is a project aiming to build a low-power secure embedded platform for Ambient ML applications. The target platform leverages RISC-V and OpenTitan, and uses the open source Renode simulation framework for pre-silicon co-development of the complete hardware and software solution. Sparrow includes a complex multi-core hardware setup with RISC-V vector instruction support as well as an advanced Rust-based software stack built on top of seL4. Various Renode capabilities have been developed to support the pre-silicon development of Sparrow, including vector instructions support, seL4 OS-aware debugging, ability to use custom, alternative CPU core models as well as various tracing and performance tracking capabilities. The open source simulation-driven development flow used by Sparrow is used to explore tradeoffs and prototype the complete solution including ML software in a continuous integration environment, and can serve as a template for other ML-focused RISC-V silicon projects of this kind.
Speakers
avatar for Michael Gielda

Michael Gielda

Vice President, Business Development & Co-Founder, Antmicro
Michael Gielda is Co-Founder at Antmicro, Chair of Outreach for CHIPS Alliance and Chair of Marketing for the Zephyr Project. He is involved in many open source software and hardware projects related to software-driven tools and methodologies, AI, FPGA & ASIC development.
KY

Kai Yick, Google

Hardware Manager, Google
Kai Yick is Hardware Manager at Google, leading the project aiming to develop an open source hardware and software platform based on RISC-V for secure and private edge ML computing.

RISC V Summit 2022 Google Antmicro AmbiML presentation pdf
Wednesday December 14, 2022 11:40am - 12:00pm PST
Grand Ballroom 220 A
  Technical, Software

11:40am PST

RISC-V Nested Virtualization - Anup Patel, Ventana Micro Systems Inc
Nested virtualization is the ability to run virtual machine (VM) instances inside other VMs. The RISC-V H-extension naturally supports nested virtualization since the H-extension functionality can be trap-n-emulated by a hypervisor for the VM running under it. This talk provides an insight into design and implementation of a nested hypervisor for the RISC-V world.
Speakers
avatar for Anup Patel

Anup Patel

Principal Software Engineer, Ventana Micro Systems
Anup Patel is an open-source enthusiast with primary interest in hypervisors, firmwares, boot-loaders, and Linux kernel. He has 17+ years of experience developing system level software and he maintains various open-source projects such as OpenSBI, KVM RISC-V, and Xvisor. He is part... Read More →

RISCV Nested Virtualization final pdf
Wednesday December 14, 2022 11:40am - 12:00pm PST
Grand Ballroom 220 C
  Technical, Software

11:40am PST

RISC-V SoC Coherency: Dealing with Unique RISC-V Coherency Issues - Adnan Hamid, Breker Verification Systems
Modern SoCs with multiple master components, complex storage architectures and advanced fabrics require exacting methods to ensure full system coherency. RISC-V presents greater challenges given its instruction flexibility, the emergence of full application processors and the varied range of potential applications. Coherency is a system problem that must be considered during processor and SoC implementations. End-to-end IP scenarios plus cache coherency, paging, interrupt management together with early firmware all adds to the verification problem, for both hardware-only sub-system test and hardware/software validation. The problem requires unique verification solutions. Breker’s test generator, based on the new Portable Stimulus standard, makes use of a broad range of algorithms to torture test the design from multiple angles. For example, leveraging the Dekker algorithm and combining this with stride testing can tease out numerous corner cases that otherwise may be missed. This talk will examine the issues of modern RISC-V SoCs, share the methods that may be used to ensure coherency, and demonstrate examples of this process on complex SoCs.
Speakers
avatar for Adnan Hamid

Adnan Hamid

CTO, Breker Verification Systems
Adnan is the founder CEO of Breker and the inventor of its core technology. Noted as the father of Portable Stimulus, he has over 20 years of experience in functional verification automation, much of it spent working in this domain. Prior to Breker, he managed AMD’s System Logic... Read More →

Wednesday December 14, 2022 11:40am - 12:00pm PST
Hall 3
  Technical, System-on-a-Chip

12:05pm PST

Introducing PathProfiler – A Hardware Mechanism to Profile Dynamic Execution - Bruce Ableidinger, SiFive
PathProfiler is a hardware mechanism for RISC-V processors to enable profilinge dynamic execution flows of a program. PathProfiler achieves this by recording control flow changes in a memory buffer, which software can read and use for dynamic optimization. PathProfiler also allows software to record micro-architectural events, such as cache misses, and this information can be used to dynamically tune programs even more aggressively. This presentation will highlight SiFive’s implementation of this functionality.
Speakers
BA

Bruce Ableidinger

Senior Architect, SiFive Inc.
President Able Engineering Advantage. Senior Architect for Debug, Trace, and Profiling at SiFive, Inc. Senior Tools Architect for MIPS LLC and a Senior Tools Architect for Imagination Technologies. MSCS Computer Science from Oregon State University and BSEE Electronic Engineering... Read More →

PathProfilerSummit2022 pdf
Wednesday December 14, 2022 12:05pm - 12:25pm PST
Hall 3
  Technical, ISA

12:05pm PST

RISC-V Power and Performance Management - Andrew Jones & Sunil V L, Ventana Micro Systems Inc.
This talk presents a high-level power and performance model for RISC-V. The ACPI specification chapters which the model is based on are presented as well as corresponding SBI extensions needed for platform support. The following SBI extensions will be presented: SRST (ratified) - enables power-off, which is an ACPI "Global State" transition, HSM (ratified) - enables ACPI's "Lower Power Idle" (LPI) states for CPU idle, SUSP (will be proposed) - enables ACPI's "Sleeping" states for system suspend, and CPPC (will be proposed) - enables ACPI's "Collaborative Processor Performance Control" for the OS to manage the performance of a logical processor on a contiguous and abstract performance scale. In addition to presenting the specifications, the current OpenSBI and Linux implementations will be demonstrated.
Speakers
avatar for Andrew Jones

Andrew Jones

Principal Software Engineer, Ventana Micro Systems Inc.
Andrew Jones (Drew) has been working with operating systems for over 18 years. Prior to Ventana Micro Systems, Drew worked on Virtualization at Red Hat for 13 years with the majority of the time leading the efforts to bring Enterprise Virt to AArch64. Now at Ventana, Drew contributes... Read More →
avatar for Sunil V L

Sunil V L

Principal Software Engineer, Ventana Micro Systems Inc.
Sunil is a software engineer at Ventana Micro Systems with 18 years of experience in Firmware and Operating Systems development. Sunil is the current acting vice-chair for the Platform Runtime Services TG and leads the UEFI/ACPI efforts for RISC-V.

RISC V Power and Performance Management pdf
Wednesday December 14, 2022 12:05pm - 12:25pm PST
Grand Ballroom 220 C
  Technical, Software

12:05pm PST

RISC-V Zkt: Portable Timing Attack Resistance (via Dynamic Taint Analysis) - Markku-Juhani O. Saarinen, PQShield Ltd.
One recently ratified RISC-V security-related extension is Zkt, the "Data Independent Execution Latency Subset." It extends the hardware-software ISA contract by defining a subset of instructions whose latency is asserted to be independent of input data. Hence these instructions can be trusted to process sensitive data without timing leakage. In the talk, I'll describe a method for verifying the constant-time behavior of RISC-V code. To accomplish the tracing of information flows, we have created a full-system RISC-V emulator that implements Dynamic Taint Analysis (DTA). Testing compiled binary executables rather than source code (or other abstract representation) is essential, as compilers are known to modify security-critical code. The simulated system has instrumentation functions for tainting sensitive variables. In the simulator, a shadow state is attached to registers and memory locations; symbolic execution and simple inference and propagation rules allow the simulator to determine which output variables are affected and where constant-time / Zkt violations can occur. We show that production-scale cryptography codebases can be analyzed for timing leakage.
Speakers
avatar for Markku-Juhani O. Saarinen

Markku-Juhani O. Saarinen

Staff Cryptography Architect, PQShield
Dr. Saarinen is a Staff Cryptography Architect at PQShield (Oxford, UK) and a Professor of Practice at Tampere University (Finland). Markku has worked as a cryptographer and security engineer for over 25 years. He joined PQShield at its inception as a University of Oxford spin-out... Read More →

20221214 riscv verifying zkt.pptx pdf
Wednesday December 14, 2022 12:05pm - 12:25pm PST
Grand Ballroom 220 B
  Technical, Security

12:25pm PST

Lunch Break
Pulled Pork - BBQ Sauce, Coleslaw, Pickles, Brioche Bun
Nashville Hot DF - Coleslaw, Chili Aioli, Brioche Bun
Kale (Vegan/GF) - Butternut Squash, Pickled Red Onion, Vinaigrette Dressing
Mac N Cheese
Coleslaw (Vegan)
Chocolate Dipped Cookie
Wednesday December 14, 2022 12:25pm - 1:50pm PST
Expo Hall - Hall 2
  Breaks + Event Experiences

12:35pm PST

Demo: Enhancing the SiFive Performance Portfolio - Drew Barbier, SiFive
Speakers
DB

Drew Barbier

Senior Director of Product Marketing, SiFive

SiFive P470 Drew RVSummit2022 pdf
Wednesday December 14, 2022 12:35pm - 12:55pm PST
Expo Hall - Hall 2 - Demo Theater
  Demo Theater

1:00pm PST

Demo: AI Solution Including AndesClarity and NN/Vector Libraries - Hubert Chung, Andes Technology
To explore the full capabilities of processors and achieve the ultimate performance, an advanced processor pipeline analyzer is needed. The talk will introduce how AndesClarity visualizes the performance and resource bottleneck to improve pipelining.
Speakers
avatar for Hubert Chung

Hubert Chung

FAE Manager,, Andes Technology
Hubert has more than 15 years of experience of software design, including embedded system, Linux device drivers, applications, and Android APK tools.

Wednesday December 14, 2022 1:00pm - 1:20pm PST
Expo Hall - Hall 2 - Demo Theater
  Demo Theater

1:25pm PST

Demo: Catapult Studio for the RTXM-2200 RISC-V CPU - Chris Owen, Imagination Technology
Join us for a look at Imagination’s new integrated development environment, Catapult Studio. Designed for the RTXM-2200 RISC-V CPU it also supports a wide range of RISC-V platforms. To meet the needs of embedded developers, the bundled SDK makes development and debugging simple, with sophisticated viewers for memory and peripheral registers as well as data visualisation tools.
Speakers
avatar for Chris Owen

Chris Owen

Senior Principal Software Engineer, Imagination Technologies
Chris Owen has worked in embedded software development at Imagination Technologies for 19 years, largely in DSP.  He now leads the team developing Imagination’s CPU Software Development Kit, Catapult SDK.

Chris Owen Summit Demo Dec 2022 pdf
Wednesday December 14, 2022 1:25pm - 1:35pm PST
Expo Hall - Hall 2 - Demo Theater
  Demo Theater

1:40pm PST

Demo: Introduction to RISC-V Verification with the Open Standard RVVI (RISC-V Verification Interface) - Aimee Sutton, Imperas Software Ltd.
Speakers
avatar for Aimee Sutton

Aimee Sutton

Director of Product Engineering, Imperas
Aimee Sutton is Director of Product Engineering at Imperas Software

Wednesday December 14, 2022 1:40pm - 1:50pm PST
Expo Hall - Hall 2 - Demo Theater
  Demo Theater

1:50pm PST

Getting the Most out of the LLVM Auto Vectorizer for RISC-V Vectors (RVV) - Kolya Panchenko, SiFive
With the RISC-V V extension reaching version 1.0 and being frozen, the focus has now shifted to software and, compiler technologies, and how to make optimal use of the scalar and vector computational units in RISC-V CPUs and SoCs. Since LLVM 14, the RISC-V target is supporting VLA autovectoriation by default, and this paves the way to further enhance the vectorizer and optimization passes. In this technical presentation, we’ll share the latest developments in LLVM vectorizer technology and how to ensure that C and C++ code get the most benefit from it. This includes learning what auto vectorization is, opportunities that the compiler looks for when translating C and C++ code into RISC-V vector instructions, how best to write new C and C++ software to resulting in optimized vector instructions. We’ll also highlight some pitfalls found in traditional C and C++ code and opportunities to address themimprove it.
Speakers
KP

Getting the Most out of the LLVM Auto Vectorizer for RISC V Vectors (RVV) pdf
Wednesday December 14, 2022 1:50pm - 2:10pm PST
Grand Ballroom 220 C
  Technical, ISA

1:50pm PST

RISC-V Perf-Model: An Open Source Cycle Accurate Performance Model for Community-wide use - Knute Lingaard, SiFive & Arup Chakraborty, Ventana Microsystems
RISC-V Performance Modeling SIG, as per its charter, drives development of open-source cycle-accurate performance models of example processor microarchitectures, for use and exploration by the RISC-V community. In this talk, we will introduce Sparta, an event driven framework for micro-architectural simulation and its relevant semantics. Next, we will introduce an end-to-end flow of an instruction trace driven configurable performance model of an example out-of-order processor, built using Sparta framework including a quick demonstration. We will further talk about our near term plan of enhancement of the model, including a list of microarchitectural features for the modeled example processor. We will end by showcasing an associated visualization tool, Helios, that consumes cycle-based performance data generated by running the model and can be used for performance analysis and debugging
Speakers
KL

Knute Lingaard

Principal Engineer, SiFive
Knute Lingaard is a Principal Engineer skilled in performance/functional modeling, software design, C++, and Python. He is the lead designer and developer of the open source GitHub project Sparcians (https://github.com/sparcians): a C++/Python project providing discrete event-driven... Read More →
avatar for Arup Chakraborty

Arup Chakraborty

Sr Staff Engineer, Ventana Micro Systems
Arup Chakraborty is currently a performance analysis engineer in Ventana Microsystems. His primary area of focus is performance analysis, performance modeling and tools & methodologies used for that purpose. Over the years, working in multiple organizations, he has contributed to... Read More →

RISC V Perf Model An open source cycle accurate Performance Model for community wide use pdf
Wednesday December 14, 2022 1:50pm - 2:10pm PST
Grand Ballroom 220 A
  Technical, Software

1:50pm PST

The OpenTitan Project - Dom Rizzo, Google
OpenTitan has brought radical transparency to silicon root of trust (RoT) development. As we approach our first commercial tapeout, this talk will update the RISC-V community on OpenTitan’s status. This talk will cover both the first discrete silicon IC along with the broader development of the OpenTitan ecosystem of compatible IP. OpenTitan IP is permissively licensed, actively maintained, and freely available on Github. Its success is made possible by the project’s focus on commercial partnerships and academic collaborations via the lowRISC Silicon Commons development environment. This has allowed us to create an ecosystem of compatible IP, including the popular Ibex 32-bit RISC-V core.
Speakers
DR

Dom Rizzo

OpenTitan TechLead/Manager, Google
Mr. Dominic Rizzo chartered the industry’s first open source silicon root of trust chip, the OpenTitan project. He serves today as the Project Director externally and is responsible for managing Google’s team of silicon, security and software engineering contributors. He is a... Read More →

Wednesday December 14, 2022 1:50pm - 2:10pm PST
Grand Ballroom 220 B
  Technical, Security

1:50pm PST

Update on Fast Interrupt Task Group (CLIC) Since Barcelona 2018 - Dan Smathers, Seagate Technology
Since Krste Asanovic last talked about the Fast Interrupt (CLIC) Task Group at the 8th RISC-V Workshop in Barcelona 2018, a lot of RISC-V interrupt architecture development has occurred. 6 Proof-of-Concept CLIC implementations have been publicly announced, PLIC specification has been frozen, Advanced Interrupt Architecture (AIA) and APLIC supporting MSI/Hypervisor specification has been frozen. And in the 2021 Summit the AIA and APLIC was presented showing application level interrupts and resumable non-maskable interrupts (RNMI) is in development. CLIC development focus has been to improve interrupt latency and throughput and provide individual interrupt configuration flexibility primarily targeting the embedded interrupt space. This talk discusses where CLIC fits and complements other RISC-V interrupt schemes, CLIC features and benefits, interrupt handler code examples such as interrupt preemption, skipping context save/restore on back-to-back interrupts, and a status update of where CLIC is in its development and its ratification schedule.
Speakers
DS

Dan Smathers

Sr. Staff Engineer, RISC-V Design Team, Seagate Technology
Dan Smathers is the Current Chair of RISC-V Fast-Interrupt Task Group. A 25-year silicon industry veteran involved in over 20 production tape-outs, Dan has implemented ARM subsystems for storage controllers for 15 years and RISC-V subsystems for 3 years. Currently he is working in... Read More →

RISC V Summit 2022 CLIC pdf
Wednesday December 14, 2022 1:50pm - 2:10pm PST
Hall 3
  Technical, ISA

2:15pm PST

Advance the Performance Analysis on RISC-V - Fei Wu & Jiangang Duan, Intel
As RISC-V moves to the high-end segment, performance analysis will become more critical. In this talk, we will introduce our pathfinding work on RISC-v performance analysis. We successfully ported the LKP (Linux* Kernel Performance – Intel) framework to RISC-V and add an initial list of representative workloads with the profiling tool enabled. With this effort, developers can easily do a performance characterization and analysis on the RISC platform to identify hardware or software bottlenecks. As an example, we will also demonstrate how to use our existing work to analyze Linux performance on RISC-V. In the future, We hope to continue advancing performance analytics with the community, including standardizing workloads, tools, and methodology.
Speakers
avatar for Fei Wu 

Fei Wu 

System Software Architect, Intel
Fei Wu is currently working for Intel on RISC-V performance analysis. He has rich experience in performance tuning for cloud applications on different architectures in Alibaba, he also spent 10+ years on Linux kernel development and maintenance in EMC, WindRiver, and Huawei.
JD

jiangang duan

RISC-V SW Engineering Director, Intel
Jiangang Duan is the RISC-V Software Engineering Director in Intel Asia-Pacific Research & Development Ltd. He has worked on data center software development and optimization for more than twenty years. His technical interests now focus on Cloud Computing, big data, and AI innovation... Read More →

advance the performance of risc v pdf
Wednesday December 14, 2022 2:15pm - 2:35pm PST
Grand Ballroom 220 C
  Technical, Software

2:15pm PST

Beating the Benchmarks: Co-evolving the ISA and Development Tools - Philipp Tomsich, VRULL GmbH
RISC-V is an open ISA that constantly evolves to address new performance needs and applications. We present an open and collaborative workflow, built on some of the core development tools (QEMU, GCC, LLVM) maintained by the RISC-V community, that shapes the evolution of the RISC-V ISA using quantitive and qualitative analysis of benchmarks and application workloads—aimed to stay ahead of evolving application requirements and beat those benchmarks. These analysis techniques used are demonstrated based on EEMBC CoreMark, the floating-point workloads of SPEC CPU 2017, and ECMAScript. Some of the more surprising results of this workflow are already becoming part of future RISC-V extensions or are integrated into our software ecosystem: novel compiler optimizations, better utilization of existing extensions, and new instructions ranging from the conditional operations of XVentanaCondOps to new floating-point instructions form the basis for RISC-V gaining a performance lead over competing architectures.
Speakers
avatar for Philipp Tomsich

Philipp Tomsich

Chief Technologist, VRULL GmbH
Dr. Philipp Tomsich is the Chief Technologist and Founder of VRULL, an engineering consultancy focused on building, enabling, and optimizing the software ecosystems for next-generation silicon solutions. Philipp brings broad experience and expertise in runtime systems (including Java... Read More →

Wednesday December 14, 2022 2:15pm - 2:35pm PST
Grand Ballroom 220 A
  Technical, Software

2:15pm PST

RISC-V and the Elf: A Story About Randomisation for Safe and Secure Critical Systems - Leonidas Kosmidis, Barcelona Supercomputing Center (BSC)
Safety-critical systems need to be safe and secure. TASA (Toolchain Agnostic Software rAndomisation) is an open source tool for C programs which allows to randomly change the binary layout of a program during compilation by performing functionally neutral source code modifications. This has multiple benefits: First, it allows the computation of Worst Case Execution Time (WCET) using Measurement Based Probabilistic Timing Analysis (MBPTA). Executables with different layouts have a different memory layout and therefore different cache performance, which results to different (and random) execution times. Moreover, changing the memory layout of the program, increases security against attacks exploiting knowledge about the memory layout i.e. stack based attacks, which jump to specific program locations. Apart from safety and security, TASA can also be used in order to find better layouts e.g. with smaller footprint or higher performance. In order to explain how TASA works, we will explain the internals of the elf binary format and we will provide experimental evidence of programs on a RISC-V platform (NOEL-V) with and without a custom RISC-V extension, using two compilers, gcc and llvm.
Speakers
avatar for Leonidas Kosmidis

Leonidas Kosmidis

Senior Researcher, Barcelona Supercomputing Center (BSC)
Dr. Leonidas Kosmidis is a Senior Researcher at the Barcelona Supercomputing Center (BSC) and faculty member at the Universitat Politecnica de Catalunya (UPC). He is the recipient of the RISC-V Educator of the Year 2019 Award, an Honourable Mention for the EuroSys Roger Needham PhD... Read More →

NOEL V and the ELF slides pdf
Wednesday December 14, 2022 2:15pm - 2:35pm PST
Grand Ballroom 220 B
  Technical, Software

2:15pm PST

The Continuum of RISC-V Compliance and Verification Testing - Simon Davidmann, Imperas Software & Allen Baum, Esperanto Technologies, Inc.
RISC-V International develops and maintains the RISC-V ISA specification and provides basic architectural tests to confirm if users have read the specification. OpenHW Group develops and maintains open-source RISC-V processor cores and develops a unified open source testbench and verifies the cores to industrial quality levels. Conceptually, verification ensures you have implemented what you have specified for your design, and the compliance testing ensures you have met the ISA specification. There is a continuum of testing. This talk discusses the boundary between compliance and design verification, and the different technologies and tools required for each area. Also, the new projects in OpenHW Group are introduced that are moving the RISC-V Verification open ecosystem forward in the areas of Functional Coverage, Verification Standards, and Core quality with quantitative measurement for use with both commercial and open-source projects. An example illustrates the new open standard RISC-V Verification Interface (RVVI) Virtual Verification Peripheral definitions (VVP) and use in compliance testing of privilege mode items such as asynchronous interrupts and debug mode requests.
Speakers
avatar for Simon Davidmann

Simon Davidmann

CEO, Imperas Software
Simon Davidmann has been working on simulators and EDA products since 1978. He is founder and CEO of Imperas and initiator of Open Virtual Platforms (www.OVPworld.org) - the place for Fast Processor Models. Simon is also the chair of the Verification Task Group of the OpenHW Group... Read More →
avatar for Allen Baum

Allen Baum

Chair of RISC-V International Architecture Test SIG, Esperanto Technologies
Allen Baum, Esperanto Technologies System ArchitectI have been involved in computer architecture for 50 years, including working on processors for HP (HPPA), Apple, ARM, DEC StrongArm and Alpha, and Intel Xeon processors.

RISC V Summit 2022 Davidmann Baum Compliance Verification pdf
Wednesday December 14, 2022 2:15pm - 2:35pm PST
Hall 3
  Technical, ISA

2:40pm PST

Introducing RISC-V Confidential Computing for IoT Devices - Bicheng Yang & Dingji Lee, Shanghai Jiao Tong University
Data security (protection of data in use) has recently emerged as an important security parameter for Internet-of-Things (IoT) devices such as smartphones, wearables, surveillance camera, drones, smart home devices, automobiles, etc., that are at the epicenter of data generation. Among other competing techniques, confidential computing is a popular mechanism prevalent in X86/ ARM platforms, that protects confidentiality/ integrity of security-sensitive applications/ data in use, by performing computation in a hardware-based attestable Trusted Execution Environment (TEE). RISC-V architecture currently lacks this capability, and we are proposing architecture for enabling confidential computing on resource-constrained IoT devices. For example, 1) IoT platforms with M/S/U-modes support but no MMU, there is no isolation between OS (S-mode) and user applications (U-mode), and 2) IoT platforms with only M-mode, there is no privilege separation between the OS and M-mode monitor code, etc., leading to data security vulnerabilities. In this talk, we introduce IoT TEE architecture and present APIs, sPMP extension, etc., to enable confidential computing for various IoT device profiles.
Speakers
BY

Bicheng Yang

Ph.D. Candidate, Shanghai Jiao Tong University
Bicheng Yang is currently a Ph.D. candidate in the Institute of Parallel And Distributed Systems (IPADS, https://ipads.se.sjtu.edu.cn/) from Shanghai Jiao Tong University (SJTU). His advisors are Prof. Yubin Xia and Prof. Haibo Chen. His research interests include operating systems... Read More →
DL

Dingji Li

Senior Ph.D. Candidate, Shanghai Jiao Tong University
Dingji Lee is currently a senior Ph.D. candidate in the Institute of Parallel And Distributed Systems (IPADS, https://ipads.se.sjtu.edu.cn/) from Shanghai Jiao Tong University (SJTU). His advisors are Prof. Haibo Chen and Prof. Binyu Zang. He primarily focuses on the security and... Read More →

Introducing RISC V Confidential Computing for IoT Devices pdf
Wednesday December 14, 2022 2:40pm - 3:00pm PST
Grand Ballroom 220 B
  Technical, Security

2:40pm PST

MiniFloat-NN: A RISC-V ISA Extension for Low-Precision NN Training - Luca Bertaccini, ETH Zürich
With neural network (NN) models getting exponentially larger, algorithmic and architectural advancements are necessary to face the new memory and compute requirements efficiently. In this context, low-precision floating-point (FP) formats play a key role as they reduce the memory footprint of NN models and open opportunities to boost the efficiency of training-oriented architectures. Such benefits drew the attention of the RISC-V community, which plans to explore new FP formats in the proposed FP SIG. We present MiniFloat-NN, a RISC-V instruction set architecture extension for low-precision NN training supporting two 16-bit and two 8-bit FP formats. The extension is based on widening sum-of-dot-products instructions and three-term additions. Such instructions are carried out on a dedicated hardware module that we integrate into an open-source FP unit. Finally, we enhance an open-source RISC-V compute cluster, which can be hierarchically replicated to build large manycore systems, with MiniFloat-NN capabilities, enabling up to a 7.2x efficiency increase with respect to the baseline system working on FP64. Our work shows the benefits of proposed lines of work for the RISC-V FP SIG.
Speakers
avatar for Luca Bertaccini

Luca Bertaccini

PhD Student, ETH Zürich
Luca Bertaccini received a Master's degree in Electronic Engineering from the University of Bologna in 2020. He is currently pursuing a PhD at the Integrated Systems Laboratory (IIS) of ETH Zurich in the Digital Systems group led by Prof. Luca Benini. His research interests include... Read More →

MiniFloat NN pdf
Wednesday December 14, 2022 2:40pm - 3:00pm PST
Grand Ballroom 220 C
  Technical, ISA

2:40pm PST

Open Standard Software Acceleration for RISC-V - Alastair Murray & Pierre-Andre Saulais, Codeplay Software
The evolution of the RISC-V V Vector extension is enabling accelerator processors that are capable of computation much faster than a CPU. Historically it has not been straightforward to design heterogeneous systems both on the software and hardware sides. There are many different software standards for parallel execution models on compute devices. These models are typically very complex due to the need to support a wide range of processors. In turn, developing a new implementation of such a compute standard can be a long and difficult process. In this presentation, we will describe a two-part approach that allows these challenges to be addressed one at a time and managed by progressively increasing scope and features. The goal of the first part is to get minimal compute kernels that have been compiled using an off-the-shelf C++ compiler to run on the accelerator under a simple compute framework. This is to manage the complexity of interfacing with the accelerator using the RVV extension. The goal of the second part is to run the same kernels using a SYCL implementation. The result of this will be demonstrated using this open standard stack on a FPGA board running a sample app.
Speakers
avatar for Alastair Murray

Alastair Murray

VP Product Engineering, Codeplay Software
Alastair is the VP of Product Engineering at Codeplay. He oversees the development of Codeplay's products, covering compilers and language runtimes for heterogeneous processors. He is also involved in the development of the OpenCL and SYCL open standards from Khronos.
PS

Pierre-Andre Saulais

Senior Principal Software Engineer, Codeplay Software
Pierre-Andre is a Senior Principal Software Engineer at Codeplay Software.

RISC V Summit 2022 Open Standard Acceleration for RISC V pdf
Wednesday December 14, 2022 2:40pm - 3:00pm PST
Grand Ballroom 220 A
  Technical, Software

3:00pm PST

Afternoon Break
Take Me Out to the Ball Game (DF)
- Corn Nuts, Sunflower Seeds, Kettle Corn, Plain Popcorn, Mindful Meat All Beef Hot Dog with Sriracha Ketchup, Grain Mustard

The Cleanse (Vegan/GF/DF)
Seaweed Snack, Green Machine Smoothie, Focus Shot Vegan/GF/DF
Wednesday December 14, 2022 3:00pm - 3:30pm PST
Expo Hall - Hall 2
  Breaks + Event Experiences

3:00pm PST

Poster Session: The RISC-V at Rice (RVR) Lab - Revamping Computer Engineering Curriculum with RISC-V - Ray Simar, Rice University
Speakers
avatar for Ray Simar

Ray Simar

Professor in the Practice, Rice University
Ray is a Professor in the Practice in Electrical and Computer Engineering at Rice University. He is a cofounder of the new RVR (RISC-V at Rice) Lab. The RVR Lab is a new experiential computer engineering research and teaching lab placing both undergraduate and graduate students at... Read More →

RISC V Poster on RVR Lab Ray V1 pdf
Wednesday December 14, 2022 3:00pm - 3:30pm PST
Expo Hall
  Poster Session
  • Slides Attached Yes

3:30pm PST

Adaptable, Scalable and Predictable Computing with a Multi-threaded RISC-V Architecture - Henk Muller, XMOS
In this session, we examine a new multi-threaded RISCV architecture, designed to deliver scalable and predictable computing to match the diverse requirements of intelligent IoT applications.
Speakers
avatar for Henk Muller

Henk Muller

CTO, XMOS
As CTO, Henk provides the strategic direction for XMOS silicon development, applications, and underpinning technologies.Prior to joining XMOS in 2009, Henk held senior Academic positions (Lecturer and Reader) at the University of Bristol, where he was involved in the research and... Read More →

XMOS Technology Session RISC V Summit 2022 pdf
Wednesday December 14, 2022 3:30pm - 3:50pm PST
Grand Ballroom 220 A
  Technical, System-on-a-Chip

3:30pm PST

Confidential Computing for RISC-V-based Platforms - Ravi Sahita, Rivos Inc.
Confidential computing aims to protect data in use on computing platforms. To achieve the goals of confidential computing, RISC-V platforms must provide a hardware-rooted, attested TCB that is able to remove all host software (OS/VMM and firmware), other tenants VMs, host software developers, operators and administrators of multi-tenant systems from the Trusted Computing Base (TCB) of tenant workloads. In this session, we cover the threat model for confidential computing and its implications on RISC-V-based platforms. We propose the major components of a Trusted Execution Environment reference architecture that scales to diverse workloads and introduce the interfaces between non-TCB and TCB components. The interfaces describes the use of the RISC-V privileged ISA to enforce confidentiality for workloads as well as the ISA and platform changes that should be considered to enforce the desired security objectives. The session will also address relevant standard protocols for attestation to inform the development of the confidential computing capability on RISC-V platforms for interoperability with other platforms.
Speakers
avatar for Ravi Sahita

Ravi Sahita

Principal Security Architect, Rivos Inc.
Ravi Sahita is a Principal Systems Security Architect at Rivos Inc. He is an expert in CPU/platform virtualization, trusted execution environments, and exploit prevention. In past work at Intel, he led security research, confidential computing (Intel TDX), exploit prevention ISA (CET... Read More →

RISC V Summit 2022 Confidential Computing for RISC V Platforms pdf
Wednesday December 14, 2022 3:30pm - 4:15pm PST
Grand Ballroom 220 C
  Technical, Security

3:30pm PST

Unified Discovery Task Group Meeting - Irma T. Flores-Mendoza, IBM
Wednesday December 14, 2022 3:30pm - 4:40pm PST
Grand Ballroom 220 B
  Technical

3:55pm PST

Panel: RISC-V in Education and Training: Successes and Gaps - Stefan Wallentowitz, Munich University of Applied Sciences; Sarah Harris, UNLV; Keith Graham, Codasip; Jenn Winikus, University at Buffalo; Ray Simar, Rice University
RISC-V has a strong academic background and was early adopted by many universities, and a industrial training partners are part of the RISC-V academia and training ecosystem. While the availability of hardware has been an issue for a couple of years, options slowly become available. This panel of distringuished members of the RISC-V education community is organized by the Special Interest Group on Academia and Training and we will briefly give an overview of the state of the ecosystem. The introduction is followed by a discussion of the available materials, tools and frameworks, along with an open discussion around gaps and challenges around education and industrial training.
Speakers
avatar for Jennifer Winikus

Jennifer Winikus

Assistant Professor of Teaching, University at Buffalo
Dr. Winikus is an Assistant Professor of Teaching at the University at Buffalo. She earned a BS and MS in Electrical Engineering from Alfred University and a MS and Ph.D. in Computer Engineering from Michigan Technological University. Her research interest is in engineering education... Read More →
avatar for Ray Simar

Ray Simar

Professor in the Practice, Rice University
Ray is a Professor in the Practice in Electrical and Computer Engineering at Rice University. He is a cofounder of the new RVR (RISC-V at Rice) Lab. The RVR Lab is a new experiential computer engineering research and teaching lab placing both undergraduate and graduate students at... Read More →
avatar for Stefan Wallentowitz

Stefan Wallentowitz

Professor, Munich University of Applied Sciences
Stefan is a professor at Munich University of Applied Sciences. He is a long term advocate and active member of the open source silicon community, most prominent in his role as director of the Free and Open Source Silicon Foundation (FOSSi Foundation). He has been active in various... Read More →
avatar for Sarah Harris

Sarah Harris

Professor, University of Nevada in Las Vegas
Dr. Harris is a Professor at the University of Nevada, Las Vegas (UNLV) in the Electrical & Computer Engineering Department. She earned her M.S. and Ph.D. at Stanford University and has worked at Hewlett Packard, Nvidia, and the Technical University of Darmstadt. Before joining the... Read More →
avatar for Keith Graham

Keith Graham

Vice President of University and Customer Experience Program, Codasip
Codasip's University Program incorporates the following three pillars:1. Preparing the next generation of researchers 2. Training the next generation of engineers 3. Developing solutions to solve tomorrow’s technological challengesIf you would like to learn more about Codasip's... Read More →

Wednesday December 14, 2022 3:55pm - 4:40pm PST
Grand Ballroom 220 A
  Technical, ISA

4:20pm PST

Security Committee Meeting - Andrew Dellow, Huawei.com
Wednesday December 14, 2022 4:20pm - 4:40pm PST
Grand Ballroom 220 C
  Technical
 
Thursday, December 15
 

8:30am PST

Registration
Thursday December 15, 2022 8:30am - 12:00pm PST
Hall 2 Foyer
  Registration

9:00am PST

Tutorial: Side-Channel Attacks and Transient Execution Vulnerabilities & RISC-V CFI - Allison Randal, Rivos & Giorgos Christou, Forth
Side Channel
An unfortunate truth of modern hardware security is that secure ISA design is not sufficient to guarantee the security of the system. Microarchitectural techniques for violating confidentiality and integrity are on the rise, including a disturbing variety of software-induced hardware attacks. The basic idea of leaking secrets through side channels has been around for a long time, but the earliest forms of these attacks were regarded as too difficult to exploit, and so were often ignored by hardware designers and vendors. Side-channel attack techniques have continued to evolve over the decades to use different channels (such as, power analysis, EM analysis, fault analysis, and timing analysis), to be easier to exploit, and to leak more information more rapidly. A series of vulnerabilities related to transient (speculative) execution rose to attention in 2018, called Spectre and Meltdown. These vulnerabilities used side-channel attack techniques, but combined them in a more sophisticated way, and with a more severe security impact, than previously considered possible. 5 years on, it turns out that Meltdown-type attacks are relatively easy to prevent with a small but intelligent change to the microarchitecture design. Spectre-type attacks have proven more difficult to tackle, not because preventing them is impossible, but because the solutions that actually work have untenable performance penalties. New varieties of transient execution vulnerabilities continue to be discovered on a regular basis, and the industry has only barely scratched the surface of vulnerabilities that are possible using new side-channel attack techniques. Consideration of microarchitecural side channels has become a necessity in modern hardware design, and vendors are faced with tough choices in the trade-offs between security, performance, power, and die area. This tutorial captures essential knowledge that every hardware engineer should have about side-channel attacks and the transient execution vulnerabilities, as well as approaches to limit their impact for CPU and SoC designers, system integrators, and end users.

CFI
Software exploitation is a major issue in computer systems for decades. Nowadays exploiting software is not as trivial as smashing the stack, but attackers come up with more and more sophisticated techniques in order to bypass deployed defenses. In this tutorial we are going to review the discussions that took part during the Control Flow Integrity Special Interest Group meetings. We will first present how the attacks evolved in order to bypass deployed defenses. Following, we will discuss notable detection and protection techniques presented in academia. Next, we will present extensions included in recent processors as well as their benefits and disadvantages. Finally, we will present a short overview of what we propose for RISC-V architecture.
Speakers
GC

Giorgos Christou

PhD student, Forth
George Christou received his BSc and MSc degree in Computer Science from the University of Crete in 2014 and 2017 respectively. He is currently a Ph.D. candidate in the Computer Science Department of University of Crete under the supervision of Prof. Sotiris Ioannidis. He has been... Read More →
AR

Allison Randal

Principal MTS, Rivos
Allison is an open source/hardware strategist. She is co-chair of the Microarchitecture Side Channels SIG at RISC-V International, a board member at the Open Infrastructure Foundation, a board member at the Software Freedom Conservancy, and a board member at Open Usage Commons. At... Read More →

RISC V Summit 2022 CFI.pptx pdf
uarch side channels pdf
Thursday December 15, 2022 9:00am - 9:55am PST
Grand Ballroom 220 B
  Tutorials

9:00am PST

Tutorial: Spike Usage and Adding A New RISC-V Extension Support to Spike - Eop Chen, SiFive
A run through of the structure of Spike would be most useful for people who would be thinking of how to add ISA extension. Walkthrough of how to add support for an extension to Spike using [insert-extension-here] as an example.
Speakers
avatar for Eop Chen

Eop Chen

Compiler Engineer, SiFive
eop Chen is a developer based in Taiwan. He is active in pushing for the formal release of RISC-V Vector C Intrinsic API. He is mainly an LLVM developer and also put his hands on other parts of RISC-V toolchain (Spike, QEMU). He likes to contribute to the open source community and... Read More →

riscv summit a tutorial talk on spike pdf
Thursday December 15, 2022 9:00am - 9:55am PST
Grand Ballroom 220 C
  Tutorials

9:00am PST

Tutorial: Running the Architectural Compatibility Tests on your Model: Theory and Practice - Neel Gala & Pawan Kumar, Incore Semiconductor
Describes what an implementor must do to run the ACTs on their model, and practical experience from an implementer (possibly break this into 2 parts). 
Speakers
avatar for Neel Gala

Neel Gala

CTO, Incore Semicoductor
Neel received his bachelors from NITW in 2010 and subsequently his PhD from IIT-Madras in 2016. His primary interests lie in Micro architecture, processor design, RISC-V, compliance and verification.Neel was amongst the founders of the SHAKTI processor program initiative at IIT-Madras... Read More →
avatar for S Pawan Kumar

S Pawan Kumar

RTL Design Engineer, InCore Semicoductors
Pawan is a RTL design Engineer at InCore Semiconductors focusing on micro-architecture improvements of a 6 stage processor and multi-core processor design. He is also one of the primary authors and maintainers of multiple tools in the Architectural Testing Eco-system of RISC-V. He... Read More →

act tutorial pdf
Thursday December 15, 2022 9:00am - 10:25am PST
Grand Ballroom 220 A
  Tutorials

10:00am PST

Tutorial: Choosing Appropriate Verification Techniques for Desired RISC-V Processor Quality - Aimee Sutton & Lee Moore, Imperas Software
As experienced SoC design verification (DV) teams take up the RISC-V processor verification challenge new approaches and techniques are required over traditional top-down block level testing. RISC-V verification plans need to address the full complexity of RISC-V features including Vector extensions, PMP security, multi-hart, multi-issue plus other advanced features. Coverage metrics have been the traditional approach to ensure a design is ready for release to prototype manufacture. For a complete RISC-V verification plan, coverage analysis needs to include all the complexities of the privilege specification including processor modes and asynchronous events. This tutorial presents a structured approach to RISC-V processor verification. It covers the basic steps from setting up an initial verification environment (testbench) to using the latest open standards for VIP (Verification IP) and the resources available within the RISC-V verification ecosystem. It highlights the importance of a verification plan and metric-driven verification for RISC-V processor designs that are destined for silicon production.
Speakers
avatar for Aimee Sutton

Aimee Sutton

Director of Product Engineering, Imperas
Aimee Sutton is Director of Product Engineering at Imperas Software
avatar for Lee Moore

Lee Moore

Lead Applications Engineer, Imperas Software
Lee Moore is the lead engineer at Imperas for RISC-V processor models and simulation tools. Prior to Imperas, Lee worked as a senior consulting engineer for EDA vendors such as Co-Design Automation and Ambit, and for ASIC vendor NEC Electronics. Lee is also a private pilot, and recently... Read More →

RV Summit2022 tutorial pdf
Thursday December 15, 2022 10:00am - 10:55am PST
Grand Ballroom 220 C
  Tutorials, Automotive

10:00am PST

Tutorial: Performance Tools - Knute Lingaard, SiFive & Arup Chakraborty, Ventana Microsystems
An overview of today’s state of the art performance tools and a look at how the working group is addressing these.
Speakers
KL

Knute Lingaard

Principal Engineer, SiFive
Knute Lingaard is a Principal Engineer skilled in performance/functional modeling, software design, C++, and Python. He is the lead designer and developer of the open source GitHub project Sparcians (https://github.com/sparcians): a C++/Python project providing discrete event-driven... Read More →
avatar for Arup Chakraborty

Arup Chakraborty

Sr Staff Engineer, Ventana Micro Systems
Arup Chakraborty is currently a performance analysis engineer in Ventana Microsystems. His primary area of focus is performance analysis, performance modeling and tools & methodologies used for that purpose. Over the years, working in multiple organizations, he has contributed to... Read More →

Thursday December 15, 2022 10:00am - 10:55am PST
Grand Ballroom 220 B
  Tutorials

10:20am PST

Morning Break
Croissants - Plain, Chocolate (V)
Smoothie
- Kale, Cucumber, Yogurt (V/GF)
- Banana, Mango, Turmeric, Oat Milk (Vegan/GF/DF)
Thursday December 15, 2022 10:20am - 11:20am PST
Grand Ballroom Foyer
  Breaks + Event Experiences

10:30am PST

Tutorial: Toolchains - Christoph Müllner, VRULL
Speakers
avatar for Christoph Müllner

Christoph Müllner

Software developer and security researcher, VRULL
Christoph Müllner is a Software Developer and IT Security Researcher at SBA Research.He has been working on compilers, managed runtimes and embedded systems for more than 13 years.His experience includes static and dynamic program analysis, profiling, benchmarking, porting, and optimizing... Read More →

Tutorial RISC V Toolchains pdf
Thursday December 15, 2022 10:30am - 12:00pm PST
Grand Ballroom 220 A
  Tutorials

11:00am PST

Tutorial: High Level Sail Overview - Bill McSpadden, RISC-V International
Overview of Sail and maybe adding 1 extension.
Speakers
avatar for Bill McSpadden

Bill McSpadden

RISC-V International
Wrangler of the RISC-V Sail model.

Summit2022GoldenModelTutorial pdf
TheSailCookbook Complete pdf
Thursday December 15, 2022 11:00am - 12:00pm PST
Grand Ballroom 220 B
  Tutorials

11:00am PST

Tutorial: Virtualization - Sandro Pinto, Universidade do Minho (Portugal)
Speakers
avatar for Sandro Pinto

Sandro Pinto

Associate Research Professor, Universidade do Minho
Sandro Pinto is an Associate Research Professor at the University of Minho, Portugal. He holds a Ph.D. in Electronics and Computer Engineering. Sandro has a deep academic background and several years of industry collaboration focusing on operating systems, virtualization, and security... Read More →

riscvsummit22 virt tuto spinto v1.0 pdf
Thursday December 15, 2022 11:00am - 12:25pm PST
Grand Ballroom 220 C
  Tutorials
 
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