-
9:30am • RISC-V FutureWatch - Imperas: The 360 Ecosystem of RISC-V - Simon Davidmann, CEO at Imperas Software and Verification Task Group Chair at OpenHW Group
-
10:00am • RISC-V FutureWatch - Ventana: Balaji Baktha, Founder and CEO, Ventana
-
11:00am • RISC-V FutureWatch - Andes Technology: Expanding the RISC-V Horizon and Beyond - Frankwell Lin, Chairman and CEO & Charlie Su, President and CTO, Andes Technology
-
11:30am • RISC-V FutureWatch - SiFive: Introducing the Horse Creek Development Board - Jack Kang, SVP, Biz Dev, CX, Corp Marketing, SiFive
-
1:30pm • RISC-V FutureWatch: Introducing a New Software-defined Silicon Capability to the RISC-V Community - Mark Lippett, XMOS
-
2:00pm • RISC-V FutureWatch: MIPS - Bringing a New Level of Scalability to RISC-V - MIPS eVocore P8700 Now Available - Itai Yaromm, VP, Sales & Marketing, MIPS Tech
-
3:00pm • RISC-V FutureWatch - Microchip: RISC-V based Mid-range FPGAs: Fueling The Edge Compute Revolution - Shakeel Peera, Vice President, Marketing and Strategy, Microchip
-
4:00pm • RISC-V General Membership Meeting (Open to all RISC-V Members)
-
11:40am • The Road Ahead - Mark Himelstein, RISC-V International
-
12:05pm • RISC-V Profiles and Profile Roadmap - Krste Asanovic, Chair, RISC-V International
-
12:30pm • OS-A SEE Explained - Aaron Durbin, Rivos Inc.
-
2:15pm • Progress in Porting Android onto RISC-V: Testing, Performance and Open Source - Mao Han, Alibaba
-
2:40pm • The RISC-V Vector Cryptography Extensions - G. Richard Newell, Microchip Technology Inc. & Ken Dockser, Rivos Inc.
-
3:05pm • I/O Virtualization Use Cases and the RISC-V IOMMU Overview - Ved Shanbhogue, Rivos Inc.
-
3:55pm • Ocelot: Open Source Vector Unit - Srikanth Arekapudi & Dongjie Xie, Tenstorrent
-
4:20pm • RISC-V for Aerospace and Defense Applications - Tom Leahy, SiFive
-
4:45pm • Real World Results using Thousands of RISC-V Cores for AI and Beyond - Dave Ditzel, Esperanto Technologies, Inc
-
11:40am • Building a Global CORE-V Cores Ecosystem - Mike Thompson, OpenHW Group
-
12:05pm • Qualification of the C and C++ Standard Libraries for Safety-critical Applications - Remi van Veen, Solid Sands B.V.
-
12:30pm • Using RISC-V in Heterogeneous Solutions to Solve Compute Challenges Presented in the Automotive Industry - Naresh Gangadharan Menon, Imagination Technologies
-
2:15pm • Is RISC-V HPC? RISC-V is HPC! - John Davis, Barcelona Supercomputing Center
-
2:40pm • RISC-V Powered SoM Based Products and HPC Native Development - Yuning Liang, Xcalibyte
-
3:05pm • Democratizing Innovation in Automotive with RISC-V and Open Source - Gordan Markuš, Canonical Ltd.
-
3:55pm • Panel: Building a Scalable RISC-V Software Ecosystem - John Hengeveld, Intel; Kumar Sankaran, Ventana; Leendert Van Doorn, Qualcomm; Steve Wanless, Red Hat; Olivier Bernard, AWS; Makeljana Shkuti, VRULL
-
11:40am • SERV: 32-bit is the New 8-bit - Olof Kindgren, Qamcom
-
12:05pm • High-Performance RISC-V Processor for Computation Acceleration and Server - Wei-han Lien, Tenstorrent Inc.
-
12:30pm • Proving RISC-V Security Model Compliance with SESIP - Eve Atallah, NXP Semiconductors
-
2:15pm • The Future of AI with RISC-V - Krste Asanovic, SiFive
-
2:40pm • Empower Upstream ML Frameworks on RISC-V - Tiejun Chen, VMware
-
3:05pm • Redefining the Embedded Development Landscape with Software-defined SoCs - Mark Lippett, XMOS
-
3:55pm • IoT True Wireless Stereo Applications Shine with RISC-V and HiFi DSP - Casey Ng, Cadence
-
4:20pm • The New Verification Ecosystem that Supports RISC-V Verification for all Adopters - Lee Moore, Imperas Software & John Sotiropoulos, Breker Verification Systems
-
4:45pm • Future is Sideways - Not Only Up and Right - John Min, Andes Technology USA
-
9:00am • Keynote: Welcome & Opening Remarks - Calista Redmond, CEO, RISC-V International
-
9:20am • Keynote: Accelerating Innovation with RISC-V: Past, Present and Future - Manju Varma, Director of Product Management, Qualcomm Technologies, Inc.
-
9:40am • Keynote: RISC-V Challenges & Opportunities - Lip-Bu Tan, Founder and Chairman, Walden International; Founding Managing Partner of Celesta Capital & Walden Catalyst Ventures; Executive Chairman, Cadence Design Systems, Inc.
-
10:00am • RISC-V Spotlight: Improving RISC-V Quality with Verification Standards and Advanced Methodologies - Simon Davidmann, CEO, Imperas Software & Verification Task Group Chair, OpenHW Group
-
10:15am • RISC-V Spotlight: Ventana Brings RISC-V to Data Center with Veyron V1 - Balaji Baktha, Founder, President, CEO and Chairman, Ventana Micro Systems
-
10:35am • RISC-V Spotlight: Delivering on Real-World Customer Challenges - Patrick Little, Chairman, President & CEO, SiFive
-
10:50am • RISC-V Spotlight: Avoiding Murphy's Law and Satan's Law Without Selling your Soul - Ron Black, CEO, Codasip
-
11:00am • RISC-V Spotlight: How RISC-V Speeds the Journey of Innovation - Bruce Weyer, Corporate Vice President, FPGA, Microchip
-
12:05pm • RISC-V Readiness for Datacenter Deployments - Balaji Baktha, Ventana Micro Systems & Mark Himelstein, RISC-V International
-
12:30pm • StarFive's Efforts in Fuelling RISC-V Software Ecosystem - See Chin Liang, StarFive Technology
-
2:15pm • A Linux Distribution’s View on RISC-V - Heinrich Schuchardt, Canonical
-
2:40pm • Introducing the Highest Performance RISC-V Development Board: Next Generation SiFive HiFive - Sam Grove, SiFive & Nikhil Krishna Gopalakrishna, Intel
-
3:05pm • Panel: It Takes a Village… to Build an Ecosystem - Amber Huffman, Google; Dan Mender, Green Hills Software; Peter Lewin, Imagination Technologies; Rob Aitken, Synopsys; Phil Dworsky, SiFive
-
11:15am • KUtrace For RISC-V - Richard Sites
-
11:40am • HW-SW Co-development for RISC-V Based Secure ML Systems with the Sparrow Project and Renode - Michael Gielda, Antmicro & Kai Yick, Google
-
1:50pm • RISC-V Perf-Model: An Open Source Cycle Accurate Performance Model for Community-wide use - Knute Lingaard, SiFive & Arup Chakraborty, Ventana Microsystems
-
2:15pm • Beating the Benchmarks: Co-evolving the ISA and Development Tools - Philipp Tomsich, VRULL GmbH
-
2:40pm • Open Standard Software Acceleration for RISC-V - Alastair Murray & Pierre-Andre Saulais, Codeplay Software
-
3:30pm • Adaptable, Scalable and Predictable Computing with a Multi-threaded RISC-V Architecture - Henk Muller, XMOS
-
3:55pm • Panel: RISC-V in Education and Training: Successes and Gaps - Stefan Wallentowitz, Munich University of Applied Sciences; Sarah Harris, UNLV; Keith Graham, Codasip; Jenn Winikus, University at Buffalo; Ray Simar, Rice University
-
9:00am • Keynote: State of the Union - Krste Asanović, Professor, UC Berkeley & Chair of RISC-V International
-
9:20am • Keynote: The Android Open Source Project and RISC-V - Lars Bergstrom, Google Director of Engineering, Android Platform Programming Languages
-
9:45am • Keynote: HPSC – Radically Advancing the Capabilities of Space-based Computing - Pete Fiacco, Member HPSC Leadership Team, JPL Consultant, Managing Partner, Executive Technology Consulting
-
10:00am • RISC-V Spotlight: Expanding the RISC-V Horizon and Beyond - Charlie Su, President and CTO, Andes Technology
-
10:20am • RISC-V Spotlight: Scrum for Success - Shreyas Derashri, VP of Compute, Imagination Technologies
-
10:30am • Keynote: Awards Presentation
-
11:40am • RISC-V SoC Coherency: Dealing with Unique RISC-V Coherency Issues - Adnan Hamid, Breker Verification Systems
-
12:05pm • Introducing PathProfiler – A Hardware Mechanism to Profile Dynamic Execution - Bruce Ableidinger, SiFive
-
1:50pm • Update on Fast Interrupt Task Group (CLIC) Since Barcelona 2018 - Dan Smathers, Seagate Technology
-
2:15pm • The Continuum of RISC-V Compliance and Verification Testing - Simon Davidmann, Imperas Software & Allen Baum, Esperanto Technologies, Inc.
